Jürgen Schlöffel

27 papers A* 1A 6B 4C 1Misc 3Journal 6Unranked 6
YearRankTypeTitle / Venue / Authors
2012 A conf
Cell-aware Production test results from a 32-nm notebook processor.
ITC
Friedrich Hapke, Michael Reese, Jason Rivers, A. Over, V. Ravikumar, Wilfried Redemund, Andreas Glowatz, Jürgen Schlöffel, Janusz Rajski
2012 B conf
Introduction to the defect-oriented cell-aware test methodology for significant reduction of DPPM rates.
ETS
Friedrich Hapke, Jürgen Schlöffel
2011 A conf
Cell-aware analysis for small-delay effects and production test results from different fault models.
ITC
Friedrich Hapke, Jürgen Schlöffel, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, Michael Reese, J. Rearick, Jason Rivers
2010 A conf
Defect-oriented cell-internal testing.
ITC
Friedrich Hapke, Wilfried Redemund, Jürgen Schlöffel, Rene Krenz-Baath, Andreas Glowatz, Michael Wittke, Hamidreza Hashempour, Stefan Eichenberger
2010 B conf
Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs.
ETS
Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler
2010 J jnl
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics.
J. Electron. Test.
Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler
2009 A conf
Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs.
ITC
Friedrich Hapke, Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel, Hamidreza Hashempour, Stefan Eichenberger, Camelia Hora, Dan Adolfsson
2009 J jnl
Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation).
it Inf. Technol.
Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille
2009 Misc conf
Restrict Encoding for Mixed-Mode BIST.
VTS
Abdul Wahid Hakmi, Stefan Holst, Hans-Joachim Wunderlich, Jürgen Schlöffel, Friedrich Hapke, Andreas Glowatz
2009 J jnl
SUPERB: Simulator utilizing parallel evaluation of resistive bridges.
ACM Trans. Design Autom. Electr. Syst.
Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian
2008 J jnl
On Acceleration of SAT-Based ATPG for Industrial Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille
2008 A conf
Resistive Bridging Fault Simulation of Industrial Circuits.
DATE
Piet Engelke, Ilia Polian, Jürgen Schlöffel, Bernd Becker
2007 C conf
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults.
MEMOCODE
Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
2007 B conf
Computation and Application of Absolute Dominators in Industrial Designs.
ETS
Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel
2007 J jnl
Deterministic logic BIST for transition fault testing.
IET Comput. Digit. Tech.
Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers
2007 — conf
Experimental Studies on SAT-Based ATPG for Gate Delay Faults.
ISMVL
Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
2007 A conf
Programmable deterministic Built-In Self-Test.
ITC
Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Christian G. Zoellin, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Laurent Souef
2007 — conf
Synthesis of irregular combinational functions with large don't care sets.
ACM Great Lakes Symposium on VLSI
Valentin Gherman, Hans-Joachim Wunderlich, R. D. Mascarenhas, Jürgen Schlöffel, Michael Garbers
2006 B conf
Deterministic Logic BIST for Transition Fault Testing.
ETS
Valentin Gherman, Hans-Joachim Wunderlich, Jürgen Schlöffel, Michael Garbers
2006 A* conf
Fault detection and diagnosis with parity trees for space compaction of test responses.
DAC
Harald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke
2006 J jnl
X-masking during logic BIST and its impact on defect coverage.
IEEE Trans. Very Large Scale Integr. Syst.
Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke
2005 — conf
A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips.
Asian Test Symposium
Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel
2005 Misc conf
ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips.
VLSI Design
Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel
2005 Misc conf
Implementing a Scheme for External Deterministic Self-Test.
VTS
Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel
2005 — conf
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits.
ISVLSI
Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
2004 — conf
Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model.
DFT
Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel
2000 — conf
PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits.
PATMOS
Andreas Herrmann, Erich Barke, Mathias Silvant, Jürgen Schlöffel