Jürgen Koehl

12 papers A* 2A 3Journal 1Unranked 6
YearRankTypeTitle / Venue / Authors
2008 — conf
Considering possible opens in non-tree topology wire delay calculation.
ACM Great Lakes Symposium on VLSI
Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl
2007 — conf
Robust wiring networks for DfY considering timing constraints.
ACM Great Lakes Symposium on VLSI
Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl
2006 A conf
DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design.
DATE
Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, Ralf Sommer, Michael Pronath, Andreas Ripp
2006 — conf
Yield Improvement by Local Wiring Redundancy.
ISQED
Jeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Müller, Sven Peyer, Christian Schulte
2003 A* conf
Designing mega-ASICs in nanogate technologies.
DAC
David E. Lackey, Paul S. Zuchowski, Jürgen Koehl
2003 — conf
IBM's 50 Million gate ASICs.
ASP-DAC
Jürgen Koehl, David E. Lackey, George W. Doerre
2001 A conf
Automatic Hierarchical Design: Fantasy or Reality? (Panel).
ICCAD
Rob A. Rutenbar, Olivier Coudert, Patrick Groeneveld, Jürgen Koehl, Scott Peterson, Vivek Raghavan, Naresh Soni
2000 — conf
Platzierungsbasierte Logikoptimierung komplexer VLSI Chips.
MBMV
Jürgen Koehl, Jürgen Schietke
1998 A conf
A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset.
DATE
Jürgen Koehl, Ulrich Baur, Thomas Ludwig, Bernhard Kick, Thomas Pflueger
1998 — conf
Analysis, reduction and avoidance of crosstalk on VLSI chips.
ISPD
Tilmann Stöhr, Markus Alt, Asmus Hetzel, Jürgen Koehl
1997 J jnl
Standard-cell-based design methodology for high-performance support chips.
IBM J. Res. Dev.
Bernhard Kick, Ulrich Baur, Jürgen Koehl, Thomas Ludwig, Thomas Pflueger
1991 A* conf
An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement.
DAC
Ren-Song Tsay, Jürgen Koehl