Jürgen Bömmels

16 papers A 1C 1Journal 5Unranked 9
YearRankTypeTitle / Venue / Authors
2025 A conf
Half-Height Double-Row CFET Standard Cells for Area Optimized Placement in A7 CMOS Node.
ICCAD
Halil Kükner, Ji-Yung Lin, Sheng Yang, Lynn Verschueren, Jürgen Bömmels, Anita Farokhnejad, Maarten Van De Put, Odysseas Zografos, Naoto Horiguchi, Geert Hellings, Marie Garcia Bardon, Julien Ryckaert
2024 — conf
Monolithic Complementary Field Effect Transistors (CFET) Demonstrated using Middle Dielectric Isolation and Stacked Contacts.
VLSI Technology and Circuits
Steven Demuynck, Victor Vega-Gonzalez, C. Toledo de Carvalho Cavalcante, L. Petersen Barbosa Lima, K. Stiers, C. Sheng, A. Vandooren, M. Hosseini, X. Zhou, Hans Mertens, Thomas Chiarella, Jürgen Bömmels, Roger Loo, E. Rosseel, Clement Porret, Y. Shimura, A. Akula, G. Mannaert, S. Choudhury, V. Brissonneau, E. Dupuy, T. Sarkar, Nathali Franchina-Vergel, A. Peter, Nicolas Jourdan, J. P. Soulie, Kevin Vandersmissen, F. Sebaai, P. Puttarame Gowda, K. Lai, A. Mingardi, S. Sumar Sarkar, K. D'Have, B. T. Chan, A. Sepulveda Marquez, R. Langer, I. Gyo Koo, E. Altamirano Sanchez, Katia Devriendt, P. Rincon Delgadillo, F. Lazzarino, Jérôme Mitard, J. Geypen, E. Grieten, D. Batuk, Y.-F. Chen, F. Verbeek, F. Holsteyns, S. Subramanian, N. Horiguchi, S. Biesemans
2023 J jnl
3D SRAM Macro Design in 3D Nanofabric Process Technology.
IEEE Trans. Circuits Syst. I Regul. Pap.
Dawit Burusie Abdi, Shairfe Muhammad Salahuddin, Jürgen Bömmels, Edouard Giacomin, Pieter Weckx, Julien Ryckaert, Geert Hellings, Francky Catthoor
2023 — conf
Integration of a Stacked Contact MOL for Monolithic CFET.
VLSI Technology and Circuits
Victor Vega-Gonzalez, D. Radisic, Bt Chan, S. Choudhury, S. Wang, A. Mingardi, Q. Toan Le, H. Decoster, Yusuke Oniki, P. Puttarame, Kevin Vandersmissen, J. P. Soulie, A. Peter, A. Sepulveda, D. Batuk, G. T. Martinez, Olivier Richard, Jürgen Bömmels, S. Biesemans, E. Dentoni Litta, Naoto Horiguchi, Seongho Park, Zsolt Tokei
2023 — conf
Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning.
VLSI Technology and Circuits
Hans Mertens, M. Hosseini, Thomas Chiarella, D. Zhou, S. Wang, G. Mannaert, E. Dupuy, D. Radisic, Z. Tao, Yusuke Oniki, Andriy Hikavyy, R. Rosseel, A. Mingardi, S. Choudhury, P. Puttarame Gowda, F. Sebaai, A. Peter, Kevin Vandersmissen, J. P. Soulie, An De Keersgieter, L. Petersen Barbosa Lima, C. Cavalcante, D. Batuk, G. T. Martinez, J. Geypen, F. Seidel, K. Paulussen, P. Favia, Jürgen Bömmels, Roger Loo, P. Wong, A. Sepulveda Marquez, B. T. Chan, Jérôme Mitard, S. Subramanian, S. Demuynck, E. Dentoni Litta, N. Horiguchi, S. Samavedam, S. Biesemans
2020 — conf
3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs.
VLSI-SoC (Selected Papers)
Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon
2020 C conf
Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow.
VLSI-SOC
Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon
2017 J jnl
Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects.
Microelectron. Reliab.
Luka Kljucar, Mario Gonzalez, Kristof Croes, Ingrid De Wolf, Joke De Messemaeker, Gayle Murdoch, Philip Nolmans, Joeri De Vos, Jürgen Bömmels, Eric Beyne, Zsolt Tökei
2016 J jnl
Design considerations for the mechanical integrity of airgaps in nano-interconnects under chip-package interaction; a numerical investigation.
Microelectron. Reliab.
Houman Zahedmanesh, Mario Gonzalez, Ivan Ciofi, Kristof Croes, Jürgen Bömmels, Zsolt Tökei
2016 J jnl
Evaluation of via density and low-k Young's modulus influence on mechanical performance of advanced node multi-level Back-End-Of-Line.
Microelectron. Reliab.
Luka Kljucar, Mario Gonzalez, Ingrid De Wolf, Kristof Croes, Jürgen Bömmels, Zsolt Tökei
2015 — conf
Constant voltage electromigration for advanced BEOL copper interconnects.
IRPS
Baojun Tang, Kris Croes, Nicolas Jourdan, Jürgen Bömmels, Zsolt Tökei, Ingrid De Wolf, Eric Wilcox, Timothy McMullen
2015 — conf
Impact of process variability on BEOL TDDB lifetime model assessment.
IRPS
Kris Croes, Deniz Kocaay, Ivan Ciofi, Jürgen Bömmels, Zsolt Tökei
2015 — conf
Intrinsic reliability of local interconnects for N7 and beyond.
IRPS
Kris Croes, Alicja Lesniewska, Chen Wu, Ivan Ciofi, Agnieszka Banczerowska, B. Briggs, S. Demuynck, Zsolt Tökei, Jürgen Bömmels, Yves Saad, W. Gao
2014 J jnl
As-grown donor-like traps in low-k dielectrics and their impact on intrinsic TDDB reliability.
Microelectron. Reliab.
Baojun Tang, Kris Croes, Yohan Barbarin, Yunqi Wang, Robin Degraeve, Yunlong Li, Maria Toledano-Luque, Thomas Kauerauf, Jürgen Bömmels, Zsolt Tökei, Ingrid De Wolf
2014 — conf
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.
ESSDERC
Trong Huynh Bao, Dmitry Yakimets, Julien Ryckaert, Ivan Ciofi, Rogier Baert, Anabela Veloso, Jürgen Bömmels, Nadine Collaert, Philippe Roussel, S. Demuynck, Praveen Raghavan, Abdelkarim Mercha, Zsolt Tokei, Diederik Verkest, Aaron Thean, Piet Wambacq
2014 — conf
Design Technology co-optimization for N10.
CICC
Julien Ryckaert, Praveen Raghavan, Rogier Baert, Marie Garcia Bardon, Mircea Dusa, Arindam Mallik, Sushil Sakhare, Boris Vandewalle, Piet Wambacq, Bharani Chava, Kris Croes, Morin Dehan, Doyoung Jang, Philippe Leray, Tsung-Te Liu, Kenichi Miyaguchi, Bertrand Parvais, Pieter Schuddinck, Philippe Weemaes, Abdelkarim Mercha, Jürgen Bömmels, Naoto Horiguchi, Greg McIntyre, Aaron Thean, Zsolt Tökei, Shaunee Cheng, Diederik Verkest, An Steegen