Jürgen Becker

610 papers A* 2A 53B 41C 52Misc 16Journal 97Unranked 326

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	DendroNN: Dendrocentric Neural Networks for Energy-Efficient Classification of Event-Based Data. CoRR Jann Krausse, Zhe Su, Kyrus Mama, Maryada, Klaus Knobloch, Giacomo Indiveri, Jürgen Becker
2026	J	`jnl`	Real-Time Stream Compaction for Sparse Machine Learning on FPGAs. CoRR Marc Neu, Isabel Haide, Torben Ferber, Jürgen Becker
2025	—	`conf`	A Pixel Histogram-Based Safety Mechanism and Fault Detection Methodology for a Robust Image Signal Processor. ACM Great Lakes Symposium on VLSI Julian Höfer, Patrick Schmidt, Hella Toto-Kiesa, Sebastian Höfer, Gregor Schewior, Dietmar Engelke, Karl-Heinz Eickel, Darius Grantz, Tanja Harbaum, Jürgen Becker
2025	J	`jnl`	A PyTorch-Compatible Spike Encoding Framework for Energy-Efficient Neuromorphic Applications. CoRR Alexandru Vasilache, Jona Scholz, Vincent Schilling, Sven Nitzsche, Florian Kälber, Johannes Korsch, Jürgen Becker
2025	—	`conf`	Automated Deployment of Real-Time Tasks for Phased Execution on Scratchpad-Based Multicore Platforms. MCSoC Konstantin Dudzik, Maximilian Kirschner, Jürgen Becker
2025	—	`conf`	BayNNgine: Hardware-Enabled Bayesian Neural Network Support for Dependable AI Inference. SOCC Julian Höfer, Fabian Lesniak, Annina Gutermann, Felix Wöran, Tanja Harbaum, Jürgen Becker
2025	—	`conf`	CH2AI: Dynamic Checkpoint Scheduling of Anytime Neural Networks on Heterogeneous Units. MCSoC Matthias Stammler, Georgios Sotiropoulos, Julian Höfer, Tanja Harbaum, Krishnendu Guha, Amlan Chakrabarti, Jürgen Becker
2025	C	`conf`	DSEParted: Co-Optimization of Embedded NPU Architectures and Neural Network Partitioning. DSD Patrick Schmidt, Fabian Krey, Alexey Serdyuk, Matthias Stammler, Tanja Harbaum, Jürgen Becker
2025	—	`conf`	Deep Neural Network Inference Partitioning in Embedded Hybrid Analog-Digital Systems. ISQED Fabian Kreß, Julian Höfer, Qiushi Lin, Patrick Schmidt, Zhenhua Zhu, Yu Zhu, Tanja Harbaum, Yu Wang, Jürgen Becker
2025	—	`conf`	Evolving Spatially Embedded Recurrent Spiking Neural Networks for Control Tasks. ICANN (4) Alexandru Vasilache, Jona Scholz, Yulia Sandamirskaya, Jürgen Becker
2025	J	`jnl`	General Compilation and Mixed-Precision Partitioning: A Combined Approach for Adaptive On-Device Learning. IEEE Trans. Very Large Scale Integr. Syst. Iuliia Topko, Fabian Kreß, Tanja Harbaum, Jürgen Becker
2025	J	`jnl`	Guest Editorial: Selected Papers From IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2024. IEEE Trans. Very Large Scale Integr. Syst. Himanshu Thapliyal, Jürgen Becker, Garrett S. Rose, Tosiron Adegbija, Selçuk Köse
2025	—	`conf`	HM2GP: A Multi-Version Task Scheduler with Extended Precedence Constraints on COTS SoCs. SOCC Matthias Stammler, Fabian Lesniak, Niraj Kumar, Arvind Easwaran, Jürgen Becker
2025	—	`conf`	Hardware-Accelerated On-Device Learning: Training, Partitioning, and Compilation for Constrained Edge AI. ISVLSI Iuliia Topko, Alexey Serdyuk, Tanja Harbaum, Jürgen Becker
2025	—	`conf`	How Activity Regularization Harms the Performance of Pruned Spiking Neural Networks. ICONS Jann Krausse, Moritz Neher, Klaus Knobloch, Jürgen Becker
2025	—	`conf`	Isolated Third-Party Applications in Existing SOME/IP-Networks. SysCon Marius Kreutzer, Austin Shinkle, Victor Pazmino Betancourt, Jürgen Becker
2025	A	`conf`	Multi-Partner Project: Open-Source Design Tools for Co-Development of AI Algorithms and AI Chips: (Initial Stage). DATE Mehdi B. Tahoori, Jürgen Becker, Jörg Henkel, Wolfgang Kunz, Ulf Schlichtmann, Georg Sigl, Jürgen Teich, Norbert Wehn
2025	J	`jnl`	MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference. CoRR Maximilian Kirschner, Konstantin Dudzik, Ben Krusekamp, Jürgen Becker
2025	—	`conf`	Programmable RFSoC-Based Antenna Emulator for MIMO System Prototyping. SOCC Christian Maximilian Karle, Johannes Pfau, Marc Neu, Kai Lukas Unger, Jürgen Becker, Andre Scheder, Tobias Kögel, Lukas Witte, Benjamin Nuss, Johann Christian Marten, Marwan Younis
2025	—	`conf`	Project-Based Hardware Design Laboratory for Undergraduates in Electrical Engineering. GeCon Christian Maximilian Karle, Iris Fürst-Walter, Florian Schade, Julian Höfer, Fabian Lesniak, Tanja Harbaum, Jürgen Becker
2025	—	`conf`	Real-Time Graph-based Point Cloud Networks on FPGAs via Stall-Free Deep Pipelining. SBCCI Marc Neu, Isabel Haide, Timo Justinger, Till Rädler, Valdrin Dajaku, Torben Ferber, Jürgen Becker
2025	—	`conf`	Realtime-Capable Hybrid Spiking Neural Networks for Neural Decoding of Cortical Activity. NICE Jann Krausse, Alexandru Vasilache, Klaus Knobloch, Jürgen Becker
2025	J	`jnl`	Realtime-Capable Hybrid Spiking Neural Networks for Neural Decoding of Cortical Activity. CoRR Jann Krausse, Alexandru Vasilache, Klaus Knobloch, Jürgen Becker
2025	J	`jnl`	SINRL: Socially Integrated Navigation with Reinforcement Learning using Spiking Neural Networks. CoRR Florian Tretter, Daniel Flögel, Alexandru Vasilache, Max Grobbel, Jürgen Becker, Sören Hohmann
2025	Misc	`conf`	Special Session - Hardware-Software Co-Design for Machine Learning Systems Made Open-Source. CODES+ISSS Mehdi B. Tahoori, Vincent Meyers, Mahboobe Sadeghipour Roodsari, Huashuangyang Xu, Jürgen Becker, Tanja Harbaum, Felix Frombach, Julian Höfer, Georgios Sotiropoulos, Jörg Henkel, Zeynep Demirdag, Heba Khdr, Hassan Nassar, Ulf Schlichtmann, Johannes Geier, Philipp van Kempen, Georg Sigl, Stefan Koegler, Matthias Probst, Jürgen Teich, Frank Hannig, Muhammad Sabih, Batuhan Sesli, Norbert Wehn, Lukas Steiner, Wolfgang Kunz, Mohamed Shelkamy Ali
2025	—	`conf`	Spiking Neural Networks for Low-Power Vibration-Based Predictive Maintenance. ICONS Alexandru Vasilache, Sven Nitzsche, Christian Kneidl, Mikael Tekneyan, Moritz Neher, Jürgen Becker
2025	J	`jnl`	Spiking Neural Networks for Low-Power Vibration-Based Predictive Maintenance. CoRR Alexandru Vasilache, Sven Nitzsche, Christian Kneidl, Mikael Tekneyan, Moritz Neher, Jürgen Becker
2025	B	`conf`	Towards a Service-Oriented Infrastructure for Distributed Systems with Heterogeneous AI Accelerators. SEAA Marius Kreutzer, Maximilian Kirschner, Jürgen Becker
2025	—	`conf`	Training Neural Networks by Optimizing Neuron Positions. Living Machines Laura Erb, Tommaso Boccato, Alexandru Vasilache, Jürgen Becker, Nicola Toschi
2025	J	`jnl`	Training Neural Networks by Optimizing Neuron Positions. CoRR Laura Erb, Tommaso Boccato, Alexandru Vasilache, Jürgen Becker, Nicola Toschi
2025	J	`jnl`	ZuSE-KI-Mobil: AI Chip Design Platform for Automotive and Industrial Applications. IEEE Trans. Very Large Scale Integr. Syst. Shaown Mojumder, Simon Friedrich, Emil Matús, Matthias Lüders, Martin Friedrich, Oliver Renke, Holger Blume, Markus Kock, Gregor Schewior, Darius Grantz, Jens Benndorf, Julian Höfer, Patrick Schmidt, Jürgen Becker, Nael Fasfous, Pierpaolo Morì, Hans-Jörg Vögel, Samira Ahmadifarsani, Leonidas Kontopoulos, Ulf Schlichtmann, Yun-Jin Li, Gerhard P. Fettweis
2024	—	`conf`	31st Reconfigurable Architectures Workshop (RAW 2024). IPDPS (Workshops) Jürgen Becker, Zhenman Fang, Viktor K. Prasanna, Marco D. Santambrogio, Ramachandran Vaidyanathan
2024	C	`conf`	A Challenge-Based Blended Learning Approach for an Introductory Digital Circuits and Systems Course. ISCAS Julian Höfer, Michael Gauß, Manuela Adams, Fabian Kreß, Fabian Kempf, Christian Maximilian Karle, Tanja Harbaum, Andreas Barth, Jürgen Becker
2024	—	`conf`	A Dynamically Pipelined Dataflow Architecture for Graph Convolutions in Real-Time Event Interpretation. SOCC Marc Neu, Christian Maximilian Karle, Patrick Schmidt, Julian Höfer, Tanja Harbaum, Jürgen Becker
2024	—	`conf`	A Full-System Approach to Multi-Valued Logic Design: (PhD Forum Paper). ASAP Annina Gutermann, Jürgen Becker
2024	—	`conf`	Automated Deep Neural Network Inference Partitioning for Distributed Embedded Systems. ISVLSI Fabian Kreß, El Mahdi El Annabi, Tim Hotfilter, Julian Höfer, Tanja Harbaum, Jürgen Becker
2024	J	`jnl`	Automated Deep Neural Network Inference Partitioning for Distributed Embedded Systems. CoRR Fabian Kreß, El Mahdi El Annabi, Tim Hotfilter, Julian Höfer, Tanja Harbaum, Jürgen Becker
2024	C	`conf`	Automated Polyhedron-based TDMA Schedule Design for Predictable Mixed-Criticality MPSoCs. DSD Matthias Stammler, Florian Schade, Jürgen Becker
2024	—	`conf`	BayWatch: Leveraging Bayesian Neural Networks for Hardware Fault Tolerance and Monitoring. DFT Julian Höfer, Matthias Stammler, Fabian Kreß, Tim Hotfilter, Tanja Harbaum, Jürgen Becker
2024	J	`jnl`	Corrigendum: Applications and techniques for fast machine learning in science. Frontiers Big Data Allison McCarn Deiana, Nhan Tran, Joshua Agar, Michaela Blott, Giuseppe Di Guglielmo, Javier M. Duarte, Philip C. Harris, Scott Hauck, Mia Liu, Mark S. Neubauer, Jennifer Ngadiuba, Seda Ogrenci-Memik, Maurizio Pierini, Thea Aarrestad, Steffen Bähr, Jürgen Becker, Anne-Sophie Berthold, Richard J. Bonventre, Tomás E. Müller-Bravo, Markus Diefenthaler, Zhen Dong, Nick Fritzsche, Amir Gholami, Ekaterina Govorkova, Dongning Guo, Kyle J. Hazelwood, Christian Herwig, Babar Khan, Sehoon Kim, Thomas Klijnsma, Yaling Liu, Kin Ho Lo, Tri Nguyen, Gianantonio Pezzullo, Seyedramin Rasoulinezhad, Ryan A. Rivera, Kate Scholberg, Justin Selig, Sougata Sen, Dmitri Strukov, William Tang, Savannah Thais, Kai Lukas Unger, Ricardo Vilalta, Belinavon Krosigk, Shen Wang, Thomas K. Warburton
2024	A	`conf`	EMDRIVE Architecture: Embedded Distributed Computing and Diagnostics from Sensor to Edge. DATE Patrick Schmidt, Iuliia Topko, Matthias Stammler, Tanja Harbaum, Jürgen Becker, Rico Berner, Omar Ahmed, Jakub Jagielski, Thomas Seidler, Markus Abel, Marius Kreutzer, Maximilian Kirschner, Victor Pazmino Betancourt, Robin Sehm, Lukas Groth, Andrija Neskovic, Rolf Meyer, Saleh Mulhem, Mladen Berekovic, Matthias Probst, Manuel Brosch, Georg Sigl, Thomas Wild, Matthias Ernst, Andreas Herkersdorf, Florian Aigner, Stefan Hommes, Sebastian Lauer, Maximilian Seidler, Thomas Raste, Gasper Skvarc Bozic, Ibai Irigoyen Ceberio, Muhammad Hassan, Albrecht Mayer
2024	—	`conf`	Embedded Multi-Core Code Generation with Cross-Layer Parallelization. PARMA-DITAM Oliver Oey, Michael Hübner, Timo Stripf, Jürgen Becker
2024	—	`conf`	Enhanced Accelerator Design for Efficient CNN Processing with Improved Row-Stationary Dataflow. ACM Great Lakes Symposium on VLSI Fabian Lesniak, Annina Gutermann, Tanja Harbaum, Jürgen Becker
2024	—	`conf`	Enhancing Force Sensing Capabilities in Exoskeleton Interfaces Using Compliant Actuator-Sensor Units - A User Study. BioRob Hosam Alagi, Nikola Fischer, Kai Behrends, Iris Fürst-Walter, Jürgen Becker, Michael Beigl, Franziska Mathis-Ullrich, Björn Hein
2024	—	`conf`	Exploring Neuronal Leakage for Spiking Neural Networks on Event-Driven Hardware. ICONS Jann Krausse, Sven Nitzsche, Brian Pachideh, Carmen Weigelt, Klaus Knobloch, Jürgen Becker
2024	J	`jnl`	Heterogeneous Accelerator Design for Multi-DNN Workloads via Heuristic Optimization. IEEE Embed. Syst. Lett. Konstantinos Balaskas, Heba Khdr, Mohammed Bakr Sikal, Fabian Kreß, Kostas Siozios, Jürgen Becker, Jörg Henkel
2024	—	`conf`	Hybrid Spiking Neural Networks for Low-Power Intra-Cortical Brain-Machine Interfaces. BioCAS Alexandru Vasilache, Jann Krausse, Klaus Knobloch, Jürgen Becker
2024	J	`jnl`	Hybrid Spiking Neural Networks for Low-Power Intra-Cortical Brain-Machine Interfaces. CoRR Alexandru Vasilache, Jann Krausse, Klaus Knobloch, Jürgen Becker
2024	—	`conf`	ICE TEA: Insertion of Custom Early Exits for Time-, Energy- & Anomaly-Aware Neural Networks. ISVLSI Matthias Stammler, Julian Höfer, Patrick Schmidt, Tanja Harbaum, Jürgen Becker
2024	—	`conf`	Improving Online Handwriting Trajectory Reconstruction Based on Temporal Convolutional Networks. SDF Alexey Serdyuk, Fabian Kreß, Iuliia Topko, Tanja Harbaum, Jürgen Becker, Tim Hamann, Peter Kämpf
2024	—	`conf`	LOTTA: An FPGA-based Low-Power Temporal Convolutional Network Hardware Accelerator. SOCC Fabian Kreß, Alexey Serdyuk, Denis Kobsar, Tim Hotfilter, Julian Höfer, Tanja Harbaum, Jürgen Becker
2024	J	`jnl`	Low-Power Vibration-Based Predictive Maintenance for Industry 4.0 using Neural Networks: A Survey. CoRR Alexandru Vasilache, Sven Nitzsche, Daniel Flögel, Tobias Schürmann, Stefan von Dosky, Thomas Bierweiler, Marvin Mußler, Florian Kälber, Sören Hohmann, Jürgen Becker
2024	J	`jnl`	Lynn Conway: Two Remembrances. IEEE Des. Test Jürgen Becker, Marilyn Wolf
2024	J	`jnl`	Machine-Learning-Based Side-Channel Attack Detection for FPGA SoCs. IEEE Trans. Circuits Syst. Artif. Intell. Lars Bauer, Hassan Nassar, Nadir Khan, Jürgen Becker, Jörg Henkel
2024	J	`jnl`	Memory Aware Design Optimisation for High-Level Synthesis. J. Signal Process. Syst. André Bannwart Perina, Jürgen Becker, Vanderlei Bonato
2024	—	`conf`	Message from the General Chairs; ISVLSI 2024. ISVLSI Himanshu Thapliyal, Jürgen Becker
2024	C	`conf`	Migration of Isolated Application Across Heterogeneous Edge Systems. ICFEC Marius Kreutzer, Maximilian Seidler, Konstantin Dudzik, Victor Pazmino Betancourt, Jürgen Becker
2024	—	`conf`	Modular Hardware Design for High-Performance MIMO-Capable SDR Systems to Accelerate 6G Development. SOCC Christian Maximilian Karle, Marc Neu, Benjamin Nuss, Jiayi Chen, Lukas Witte, Andre Scheder, Tanja Harbaum, Jürgen Becker
2024	—	`conf`	On Metric-Driven Development of Embedded Neuromorphic AI. SOCC Jann Krausse, Moritz Neher, Iris Fürst-Walter, Carmen Weigelt, Tanja Harbaum, Klaus Knobloch, Jürgen Becker
2024	Misc	`conf`	Ph.D. Project: Compiler-Driven Hardware/Software Co- Design for Embedded AI. FCCM Patrick Schmidt, Jürgen Becker
2024	—	`conf`	RVVe: A Minimal RISC-V Vector Processor for Embedded AI Acceleration. SOCC Patrick Schmidt, Johannes Pfau, Tim Hotfilter, Matthias Stammler, Tanja Harbaum, Jürgen Becker
2024	J	`jnl`	Real-Time Graph Building on FPGAs for Machine Learning Trigger Applications in Particle Physics. Comput. Softw. Big Sci. Marc Neu, Jürgen Becker, Philipp Dorwarth, Torben Ferber, Lea Reuter, Slavomira Stefkova, Kai Lukas Unger
2024	—	`conf`	Scalable Multi-Level Synchronization Technique of Distributed Multi-RFSoC-Server Systems for 6G. SOCC Christian Maximilian Karle, Marc Neu, Benjamin Nuss, Lukas Witte, Andre Scheder, Eva Waldner, Ema Shkurtaj, Tanja Harbaum, Jürgen Becker
2024	—	`conf`	Towards a General Compilation Approach for On-device Training in Embedded Systems. NorCAS Iuliia Topko, Tanja Harbaum, Jürgen Becker
2024	A	`conf`	UNCOVER: Data-Driven Design Support through Continuous Monitoring of Security Incidents. DATE Matthias Stammler, Julian Lorenz, Eric Sax, Jürgen Becker, Matthias Hamann, Patrick Bidinger, Andreas Dewald, Paraskevi Georgouti, Alexios Camarinopoulos, Günter Becker, Klaus Finsterbusch, Maximilian Kirschner, Laurenz Adolph, Carl Philipp Hohl, Maria Rill, Daniel Vonderau, Victor Pazmino Betancourt
2024	—	`conf`	VHDL Crash Course: A Multimedia-Based Teaching Approach. GeCon Fabian Kreß, Vladimir Sidorenko, Iuliia Topko, Kai Lukas Unger, Tanja Harbaum, Jürgen Becker
2024	A	`conf`	Work in Progress: Predictable Execution of Isolated Real-Time Tasks on Multicore Systems Using the LET Paradigm. RTAS Konstantin Dudzik, Maximilian Kirschner, Victor Pazmino Betancourt, Jürgen Becker
2024	A	`conf`	Work-in-Progress: Real-Time Neural Network Inference on a Custom RISC-V Multicore Vector Processor. RTSS Maximilian Kirschner, Konstantin Dudzik, Jürgen Becker
2024	J	`jnl`	Work-in-Progress: Real-Time Neural Network Inference on a Custom RISC-V Multicore Vector Processor. CoRR Maximilian Kirschner, Konstantin Dudzik, Jürgen Becker
2024	A	`conf`	XANDAR: An X-by-Construction Framework for Safety, Security, and Real-Time Behavior of Embedded Software Systems. DATE Tobias Dörr, Florian Schade, Jürgen Becker, Georgios Keramidas, Nikos Petrellis, Vasilios I. Kelefouras, Michail Mavropoulos, Konstantinos Antonopoulos, Christos P. Antonopoulos, Nikolaos S. Voros, Alexander Ahlbrecht, Wanja Zaeske, Vincent Janson, Phillip Nöldeke, Umut Durak, Christos Panagiotou, Dimitris Karadimas, Nico Adler, Clemens Reichmann, Andreas Sailer, Raphael Weber, Thomas Wilhelm, Wolfgang Gabler, Katrin Weiden, Xavier Anzuela Recasens, Sakir Sezer, Fahad Siddiqui, Rafiullah Khan, Kieran McLaughlin, Sena Yengec Tasdemir, Balmukund Sonigara, Henry Hui, Esther Soriano Viguer, Aridane Álvarez Suárez, Vicente Nicolau Gallego, Manuel Muñoz Alcobendas, Miguel Masmano Tello
2024	—	`conf`	ZuSE-KI-Mobil AI Chip Design Platform: An Overview. NorCAS Shaown Mojumder, Simon Friedrich, Emil Matús, Gerhard P. Fettweis, Matthias Lüders, Martin Friedrich, Oliver Renke, Holger Blume, Julian Höfer, Patrick Schmidt, Jürgen Becker, Darius Grantz, Markus Kock, Jens Benndorf, Nael Fasfous, Pierpaolo Morì, Hans-Jörg Vögel, Samira Ahmadifarsani, Leonidas Kontopoulos, Ulf Schlichtmann, Kay Bierzynski
2023	—	`ed.`	36th IEEE International System-on-Chip Conference, SOCC 2023, Santa Clara, CA, USA, September 5-8, 2023 SOCC Jürgen Becker, Andrew Marshall, Tanja Harbaum, Amlan Ganguly, Fahad Siddiqui, Kieran McLaughlin
2023	—	`conf`	A Convolution Neural Network Based Displaced Vertex Trigger for the Belle II Experiment. ARC Kai Lukas Unger, Jürgen Becker, Christian Kiesling, Yichuan Ma, Felix Meggendorfer, Marc Neu, Elia Schmidt, Ulrike Zweigart
2023	C	`conf`	A Hardware-Aware Sampling Parameter Search for Efficient Probabilistic Object Detection. ICVS Julian Höfer, Tim Hotfilter, Fabian Kreß, Chen Qiu, Tanja Harbaum, Jürgen Becker
2023	—	`conf`	A Hardware-Centric Approach to Increase and Prune Regular Activation Sparsity in CNNs. AICAS Tim Hotfilter, Julian Höfer, Fabian Kreß, Fabian Kempf, Leonhard Kraft, Tanja Harbaum, Jürgen Becker
2023	—	`conf`	A Low-Stall Methodology for an Interleaved Processor State Replication. MCSoC Fabian Kempf, Julian Höfer, Tim Hotfilter, Jürgen Becker
2023	—	`conf`	A Scalable and Cost-Efficient Antenna Testbed Using FPGA-Server Compound Structures for Prototyping 6G Applications. DCOSS-IoT Marc Neu, Christian Maximilian Karle, Benjamin Nuss, Patrick Gröschel, Jürgen Becker
2023	C	`conf`	A Unified SoC Lab Course: Combined Teaching of Mixed Signal Aspects, System Integration, Software Development and Documentation. ISCAS Johannes Pfau, Richard Leys, Marc Neu, Alexey Serdyuk, Ivan Peric, Jürgen Becker
2023	C	`conf`	ATLAS: An Approximate Time-Series LSTM Accelerator for Low-Power IoT Applications. DSD Fabian Kreß, Alexey Serdyuk, Micha Hiegle, Disnebio Waldmann, Tim Hotfilter, Julian Höfer, Tim Hamann, Jens Barth, Peter Kämpf, Tanja Harbaum, Jürgen Becker
2023	—	`conf`	An Analytical Model of Configurable Systolic Arrays to find the Best-Fitting Accelerator for a given DNN Workload. DroneSE/RAPIDO@HiPEAC Tim Hotfilter, Patrick Schmidt, Julian Höfer, Fabian Kreß, Tanja Harbaum, Jürgen Becker
2023	—	`conf`	Approximate Accelerators: A Case Study using Runtime Reconfigurable Processors. SOCC Fabian Lesniak, Tanja Harbaum, Jürgen Becker
2023	—	`conf`	Automated Replacement of State-Holding Flip-Flops to Enable Non-Volatile Checkpointing. NorCAS Fabian Kreß, Johannes Pfau, Fabian Kempf, Patrick Schmidt, Zhuofan He, Tanja Harbaum, Jürgen Becker
2023	C	`conf`	Automatic Deployment of Embedded Real-Time Software Systems to Hypervisor-Managed Platforms. DSD Florian Schade, Tobias Dörr, Alexander Ahlbrecht, Vincent Janson, Umut Durak, Jürgen Becker
2023	J	`jnl`	CNNParted: An open source framework for efficient Convolutional Neural Network inference partitioning in embedded systems. Comput. Networks Fabian Kreß, Vladimir Sidorenko, Patrick Schmidt, Julian Höfer, Tim Hotfilter, Iris Walter, Tanja Harbaum, Jürgen Becker
2023	—	`conf`	Characterization of Execution Time Variability in FPGA-Based AI-Accelerators. DASC/PiCom/CBDCom/CyberSciTech Maximilian Kirschner, Federico Nicolás Peccia, Felix Thömmes, Victor Pazmino Betancourt, Oliver Bringmann, Jürgen Becker
2023	—	`conf`	Co-Simulating Region-Based Dynamic Voltage Scaling for FPGA Architecture Design. NorCAS Johannes Pfau, Jiro Hernandez, Maximilian Reuter, Klaus Hofmann, Jürgen Becker
2023	—	`conf`	Context-Aware Layer Scheduling for Seamless Neural Network Inference in Cloud-Edge Systems. MCSoC Matthias Stammler, Vladimir Sidorenko, Fabian Kreß, Patrick Schmidt, Jürgen Becker
2023	—	`conf`	DREAM: Distributed Reinforcement Learning Enabled Adaptive Mixed-Critical NoC. ISVLSI Nidhi Anantharajaiah, Yunhe Xu, Fabian Lesniak, Tanja Harbaum, Jürgen Becker
2023	A	`conf`	Design Space Exploration on Efficient and Accurate Human Pose Estimation from Sparse IMU-Sensing. IROS Iris Fürst-Walter, Antonio Nappi, Tanja Harbaum, Jürgen Becker
2023	J	`jnl`	Design Space Exploration on Efficient and Accurate Human Pose Estimation from Sparse IMU-Sensing. CoRR Iris Fürst-Walter, Antonio Nappi, Tanja Harbaum, Jürgen Becker
2023	—	`conf`	EFFECT: An End-to-End Framework for Evaluating Strategies for Parallel AI Anomaly Detection. INNS DLIA@IJCNN Matthias Stammler, Julian Höfer, David Kraus, Patrick Schmidt, Tim Hotfilter, Tanja Harbaum, Jürgen Becker
2023	—	`conf`	Embedded reliable HPC Integration enabling smart Automotive & IoT Systems. MECO Jürgen Becker
2023	—	`conf`	European Processor Initiative Demonstration of Integrated Semi-Autonomous Driving System. SOCC Daniel Hofman, Mario Brcic, Mihael Kovac, Tim Hotfilter, Jürgen Becker, Dominik Reinhardt, Sorin Mihai Grigorescu, R. Stevens, T. T. Vo
2023	—	`conf`	LETSCOPE: Lifecycle Extensions Through Software-Defined Predictive Control of Power Electronics. EUROCON Anqi Chu, Chris Manuel Hermann, Johannes Silz, Johannes Pfau, Kevin Muñoz Barón, Nidhi Anantharajaiah, Patrick Schmidt, Tim Hotfilter, Xiang Xie, Jürgen Becker, Ingmar Kallfass, Jörg Roth-Stielow, Wilhelm Stork
2023	—	`conf`	Leveraging Adaptive Redundancy in Multi-Core Processors for Realizing Adaptive Fault Tolerance in Mixed-Criticality Systems. MECO Fabian Kempf, Jürgen Becker
2023	—	`conf`	Leveraging Mixed-Precision CNN Inference for Increased Robustness and Energy Efficiency. SOCC Tim Hotfilter, Julian Höfer, Philipp Merz, Fabian Kreß, Fabian Kempf, Tanja Harbaum, Jürgen Becker
2023	—	`conf`	Low-Power Traffic Surveillance using Multiple RGB and Event Cameras: A Survey. ISC2 Tobias Fleck, Svetlana Pavlitska, Sven Nitzsche, Brian Pachideh, Federico Nicolás Peccia, Soikat Hasan Ahmed, Svea Marie Meyer, Mathis Richter, Kevin Broertjes, Emre Neftci, Jürgen Becker, Oliver Bringmann, J. Marius Zöllner
2023	—	`conf`	Low-latency inter-domain communication on the Xen hypervisor. MCSoC Fabian Lesniak, Tanja Harbaum, Jürgen Becker
2023	C	`conf`	Mitigating Masking in Automotive Communication Systems: Modeling and Hardware Generation. DSD Matthias Stammler, Matthias Hamann, Tanja Harbaum, Jürgen Becker
2023	—	`conf`	Multilevel Security Model for Secure Information Flow Inside Software Components Employing Automated Code Generation. MECO Matthias Stammler, Matthias Hamann, Jürgen Becker
2023	—	`conf`	Non-Intrusive Runtime Monitoring for Manycore Prototypes. DroneSE/RAPIDO@HiPEAC Fabian Lesniak, Nidhi Anantharajaiah, Tanja Harbaum, Jürgen Becker
2023	B	`conf`	Pattern-Based Information Flow Control for Safety-Critical On-Chip Systems. SAFECOMP Tobias Dörr, Florian Schade, Jürgen Becker
2023	—	`conf`	Policy Model for Task Reallocation at Runtime in Edge Computing Infrastructures. IoTaIS Victor Pazmino Betancourt, Maximilian Kirschner, Marius Kreutzer, Jürgen Becker
2023	C	`conf`	Policy-Based Task Allocation at Runtime for a Self-Adaptive Edge Computing Infrastructure. ISADS Victor Pazmino Betancourt, Maximilian Kirschner, Marius Kreutzer, Jürgen Becker
2023	Misc	`conf`	ReLoDAQ: Resource-Efficient, Low-Overhead 200 Gbits FCCM Christian Maximilian Karle, Marc Neu, Johannes Pfau, Jan Sperling, Jürgen Becker
2023	—	`conf`	Reinforcement Learning Enabled Multi-Layered NoC for Mixed Criticality Systems. MCSoC Nidhi Anantharajaiah, Fabian Lesniak, Tanja Harbaum, Jürgen Becker
2023	—	`conf`	SiFI-AI: A Fast and Flexible RTL Fault Simulation Framework Tailored for AI Models and Accelerators. ACM Great Lakes Symposium on VLSI Julian Höfer, Fabian Kempf, Tim Hotfilter, Fabian Kreß, Tanja Harbaum, Jürgen Becker
2023	A	`conf`	The ZuSE-KI-Mobil AI Accelerator SoC: Overview and a Functional Safety Perspective. DATE Fabian Kempf, Julian Höfer, Tanja Harbaum, Jürgen Becker, Nael Fasfous, Alexander Frickenstein, Hans-Jörg Vögel, Simon Friedrich, Robert Wittig, Emil Matús, Gerhard P. Fettweis, Matthias Lüders, Holger Blume, Jens Benndorf, Darius Grantz, Martin Zeller, Dietmar Engelke, Karl-Heinz Eickel
2023	—	`conf`	Towards Hardware-Software Self-Adaptive Acceleration of Spiking Neural Networks on Reconfigurable Digital Hardware. SOCC Brian Pachideh, Christian Zielke, Sven Nitzsche, Jürgen Becker
2023	—	`conf`	Towards the on-device Handwriting Trajectory Reconstruction of the Sensor Enhanced Pen. WF-IoT Alexey Serdyuk, Fabian Kreß, Micha Hiegle, Tanja Harbaum, Jürgen Becker, Florent Imbert, Yann Soullard, Romain Tavenard, Éric Anquetil, Jens Barth, Peter Kämpf
2023	Misc	`conf`	Work-in-Progress: Integrating WebAssembly into Service-Oriented Architectures for Edge Systems. EMSOFT Marius Kreutzer, Maximilian Seidler, Victor Pazmino Betancourt, Jürgen Becker
2022	—	`conf`	29th Reconfigurable Architectures Workshop (RAW 2022). IPDPS Workshops Jürgen Becker, Lana Josipovic, Viktor K. Prasanna, Marco D. Santambrogio, Ramachandran Vaidyanathan
2022	—	`ed.`	35th IEEE International System-on-Chip Conference, SOCC 2022, Belfast, United Kingdom, September 5-8, 2022 SOCC Sakir Sezer, Thomas Büchner, Jürgen Becker, Andrew Marshall, Fahad Siddiqui, Tanja Harbaum, Kieran McLaughlin
2022	C	`conf`	A Behavior Specification and Simulation Methodology for Embedded Real-Time Software. DS-RT Tobias Dörr, Florian Schade, Alexander Ahlbrecht, Wanja Zaeske, Leonard Masing, Umut Durak, Jürgen Becker
2022	—	`conf`	A hardware/software co-design approach to prototype 6G mobile applications inside the GNU Radio SDR Ecosystem using FPGA hardware accelerators. HEART Christian Maximilian Karle, Marius Kreutzer, Johannes Pfau, Jürgen Becker
2022	C	`conf`	A holistic hardware-software approach for fault-aware embedded systems. DSD Fabian Kempf, Christoph Kühbacher, Christian Mellwig, Sebastian Altmeyer, Theo Ungerer, Jürgen Becker
2022	C	`conf`	Adaptive Exploration Based Routing for Spatial Isolation in Mixed Criticality Systems. DSD Nidhi Anantharajaiah, Jürgen Becker
2022	A	`conf`	AnaCoNGA: Analytical HW-CNN Co-Design Using Nested Genetic Algorithms. DATE Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Emanuele Valpreda, Driton Salihu, Julian Höfer, Anmol Singh, Naveen Shankar Nagaraja, Hans-Jörg Vögel, Nguyen Anh Vu Doan, Maurizio Martina, Jürgen Becker, Walter Stechele
2022	J	`jnl`	Applications and Techniques for Fast Machine Learning in Science. Frontiers Big Data Allison McCarn Deiana, Nhan Tran, Joshua Agar, Michaela Blott, Giuseppe Di Guglielmo, Javier M. Duarte, Philip C. Harris, Scott Hauck, Mia Liu, Mark S. Neubauer, Jennifer Ngadiuba, Seda Ogrenci Memik, Maurizio Pierini, Thea Aarrestad, Steffen Bähr, Jürgen Becker, Anne-Sophie Berthold, Richard J. Bonventre, Tomás E. Müller-Bravo, Markus Diefenthaler, Zhen Dong, Nick Fritzsche, Amir Gholami, Ekaterina Govorkova, Dongning Guo, Kyle J. Hazelwood, Christian Herwig, Babar Khan, Sehoon Kim, Thomas Klijnsma, Yaling Liu, Kin Ho Lo, Tri Nguyen, Gianantonio Pezzullo, Seyedramin Rasoulinezhad, Ryan A. Rivera, Kate Scholberg, Justin Selig, Sougata Sen, Dmitri Strukov, William Tang, Savannah Thais, Kai Lukas Unger, Ricardo Vilalta, Belinavon Krosigk, Shen Wang, Thomas K. Warburton
2022	—	`conf`	Automated Search for Deep Neural Network Inference Partitioning on Embedded FPGA. PKDD/ECML Workshops (1) Fabian Kreß, Julian Höfer, Tim Hotfilter, Iris Walter, El Mahdi El Annabi, Tanja Harbaum, Jürgen Becker
2022	—	`conf`	Data Movement Reduction for DNN Accelerators: Enabling Dynamic Quantization Through an eFPGA. ISVLSI Tim Hotfilter, Fabian Kreß, Fabian Kempf, Jürgen Becker, Imen Baili
2022	C	`conf`	Hardware Support for Predictable Resource Sharing in Virtualized Heterogeneous Multicores. DSD Timo Sandmann, Jürgen Becker
2022	B	`conf`	Hardware-aware Partitioning of Convolutional Neural Network Inference for Embedded AI Applications. DCOSS Fabian Kreß, Julian Höfer, Tim Hotfilter, Iris Walter, Vladimir Sidorenko, Tanja Harbaum, Jürgen Becker
2022	—	`conf`	Hardware-aware Workload Distribution for AI-based Online Handwriting Recognition in a Sensor Pen. MECO Fabian Kreß, Alexey Serdyuk, Tim Hotfilter, Julian Höfer, Tanja Harbaum, Jürgen Becker, Tim Hamann
2022	—	`conf`	Hypervisor-Based Target Deployment Strategies for Time Predictability in Model-Based Development. SOCC Florian Schade, Tobias Dörr, Jürgen Becker
2022	J	`jnl`	Lifecycle Management of Automotive Safety-Critical Over the Air Updates: A Systems Approach. IEEE Access Houssem Guissouma, Carl Philipp Hohl, Fabian Lesniak, Marc Schindewolf, Jürgen Becker, Eric Sax
2022	C	`conf`	PREUNN: Protocol Reverse Engineering using Neural Networks. ICISSP Valentin Kiechle, Matthias Börsig, Sven Nitzsche, Ingmar Baumgart, Jürgen Becker
2022	—	`conf`	Runtime Adaptive Cache Checkpointing for RISC Multi-Core Processors. SOCC Fabian Kempf, Julian Höfer, Fabian Kreß, Tim Hotfilter, Tanja Harbaum, Jürgen Becker
2022	—	`conf`	Safety by Construction: Pattern-Based Application of Safety Mechanisms in XANDAR. ISVLSI Tobias Dörr, Florian Schade, Leonard Masing, Jürgen Becker, Georgios Keramidas, Christos P. Antonopoulos, Michail Mavropoulos, Vasilios I. Kelefouras, Nikolaos S. Voros
2022	J	`jnl`	The impact of formulation of cost function in Task Mapping Problem on NoCs using bio-inspired based-metaheuristics. Microprocess. Microsystems Jessé Barreto de Barros, Nidhi Anantharajaiah, Mauricio Ayala-Rincón, Carlos Humberto Llanos Quintero, Jürgen Becker
2022	A	`conf`	Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCs. DATE Tim Hotfilter, Fabian Kreß, Fabian Kempf, Jürgen Becker, Juan Miguel De Haro Ruiz, Daniel Jiménez-González, Miquel Moretó, Carlos Álvarez, Jesús Labarta, Imen Baili
2022	B	`conf`	Using Trace Data for Run-Time Optimization of Parallel Execution in Real-Time Multi-Core Systems. RTCSA Florian Schade, Timo Sandmann, Jürgen Becker, Henrik Theiling
2022	J	`jnl`	V-FPGAs: Increasing Performance with Manual Placement, Timing Extraction and Extended Timing Modeling. J. Signal Process. Syst. Johannes Pfau, Peter Wagih Zaki, Jürgen Becker
2022	—	`conf`	XANDAR: A holistic Cybersecurity Engineering Process for Safety-critical and Cyber-physical Systems. VTC Spring Fahad Siddiqui, Rafiullah Khan, Sakir Sezer, Kieran McLaughlin, Leonard Masing, Tobias Dörr, Florian Schade, Jürgen Becker, Alexander Ahlbrecht, Wanja Zaeske, Umut Durak, Nico Adler, Andreas Sailer, Raphael Weber, Thomas Wilhelm, Géza Németh, Victor Morales, Paco Gomez, Georgios Keramidas, Christos P. Antonopoulos, Michail Mavropoulos, Vasilios I. Kelefouras, Konstantinos Antonopoulos, Nikolaos S. Voros, Christos Panagiotou, Dimitris Karadimas
2022	A	`conf`	XANDAR: Exploiting the X-by-Construction Paradigm in Model-based Development of Safety-critical Systems. DATE Leonard Masing, Tobias Dörr, Florian Schade, Jürgen Becker, Georgios Keramidas, Christos P. Antonopoulos, Michail Mavropoulos, Efstratios Tiganourias, Vasilios I. Kelefouras, Konstantinos Antonopoulos, Nikolaos S. Voros, Umut Durak, Alexander Ahlbrecht, Wanja Zaeske, Christos Panagiotou, Dimitris Karadimas, Nico Adler, Andreas Sailer, Raphael Weber, Thomas Wilhelm, Géza Németh, Fahad Siddiqui, Rafiullah Khan, Vahid Garousi, Sakir Sezer, Victor Morales
2021	J	`jnl`	A Hybrid Prototyping Framework in a Virtual Platform Centered Design and Verification Flow. IEEE Embed. Syst. Lett. Leonard Masing, Fabian Lesniak, Jürgen Becker
2021	J	`jnl`	Achieving cost-efficient fail-operational behavior based on inherent redundancy at the system level. Microprocess. Microsystems Tobias Dörr, Timo Sandmann, Patrick Friederich, Arnd Leitner, Jürgen Becker
2021	—	`conf`	An Adaptive Lockstep Architecture for Mixed-Criticality Systems. ISVLSI Fabian Kempf, Thomas Hartmann, Steffen Baehr, Jürgen Becker
2021	—	`conf`	Ant Colony Optimization Based NoCs for Flexible Spatial Isolation in Mixed Criticality Systems. SoCC Nidhi Anantharajaiah, Felix Knopf, Jürgen Becker
2021	J	`jnl`	Applications and Techniques for Fast Machine Learning in Science. CoRR Allison McCarn Deiana, Nhan Tran, Joshua Agar, Michaela Blott, Giuseppe Di Guglielmo, Javier M. Duarte, Philip C. Harris, Scott Hauck, Mia Liu, Mark S. Neubauer, Jennifer Ngadiuba, Seda Ogrenci Memik, Maurizio Pierini, Thea Aarrestad, Steffen Bähr, Jürgen Becker, Anne-Sophie Berthold, Richard J. Bonventre, Tomás E. Müller-Bravo, Markus Diefenthaler, Zhen Dong, Nick Fritzsche, Amir Gholami, Ekaterina Govorkova, Kyle J. Hazelwood, Christian Herwig, Babar Khan, Sehoon Kim, Thomas Klijnsma, Yaling Liu, Kin Ho Lo, Tri Nguyen, Gianantonio Pezzullo, Seyedramin Rasoulinezhad, Ryan A. Rivera, Kate Scholberg, Justin Selig, Sougata Sen, Dmitri Strukov, William Tang, Savannah Thais, Kai Lukas Unger, Ricardo Vilalta, Belinavon Krosigk, Thomas K. Warburton, Maria Acosta Flechas, Anthony Aportela, Thomas Calvet, Leonardo Cristella, Daniel Diaz, Caterina Doglioni, Maria Domenica Galati, Elham E Khoda, Farah Fahim, Davide Giri, Benjamin Hawks, Duc Hoang, Burt Holzman, Shih-Chieh Hsu, Sergo Jindariani, Iris Johnson, Raghav Kansal, Ryan Kastner, Erik Katsavounidis, Jeffrey D. Krupa, Pan Li, Sandeep Madireddy, Ethan Marx, Patrick McCormack, Andres Meza, Jovan Mitrevski, Mohammed Attia Mohammed, Farouk Mokhtar, Eric A. Moreno, Srishti Nagu, Rohin Narayan, Noah Palladino, Zhiqiang Que, Sang Eon Park, Subramanian Ramamoorthy, Dylan S. Rankin, Simon Rothman, Ashish Sharma, Sioni Summers, Pietro Vischia, Jean-Roch Vlimant, Olivia Weng
2021	J	`jnl`	Automatic Floorplanning and Standalone Generation of Bitstream-Level IP Cores. IEEE Trans. Very Large Scale Integr. Syst. Nadir Khan, Jorge Castro-Godínez, Shixiang Xue, Jörg Henkel, Jürgen Becker
2021	A*	`conf`	Binary-LoRAX: Low-Latency Runtime Adaptable XNOR Classifier for Semi-Autonomous Grasping with Prosthetic Hands. ICRA Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Mohamed Badawy, Felix Hundhausen, Julian Höfer, Naveen Shankar Nagaraja, Christian Unger, Hans-Jörg Vögel, Jürgen Becker, Tamim Asfour, Walter Stechele
2021	—	`conf`	Embedded Face Recognition for Personalized Services in the Assistive Robotics. PKDD/ECML Workshops (1) Iris Walter, Jonas Ney, Tim Hotfilter, Vladimir Rybalkin, Julian Höfer, Norbert Wehn, Jürgen Becker
2021	C	`conf`	Employing the Concept of Multilevel Security to Generate Access Protection Configurations for Automotive On-Board Networks. DSD Tobias Dörr, Timo Sandmann, Hannes Mohr, Jürgen Becker
2021	—	`conf`	Evaluation of Different Manual Placement Strategies to Ensure Uniformity of the V-FPGA. ARC Johannes Pfau, Peter Wagih Zaki, Jürgen Becker
2021	—	`conf`	Evaluation of a Hypervisor-Based Smart Controller for Industry 4.0 Functions in Manufacturing. WF-IoT Florian Schade, David Barton, Jürgen Fleischer, Jürgen Becker
2021	—	`conf`	FLECSim-SoC: A Flexible End-to-End Co-Design Simulation Framework for System on Chips. SoCC Tim Hotfilter, Julian Höfer, Fabian Kreß, Fabian Kempf, Jürgen Becker
2021	J	`jnl`	Fast Resource and Timing Aware Design Optimisation for High-Level Synthesis. IEEE Trans. Computers André B. Perina, Arthur Silitonga, Jürgen Becker, Vanderlei Bonato
2021	J	`jnl`	From MOSFETs to Ambipolar Transistors: Standard Cell Synthesis for the Planar RFET Technology. IEEE Trans. Circuits Syst. I Regul. Pap. Maximilian Reuter, Johannes Pfau, Tillmann A. Krauss, Jürgen Becker, Klaus Hofmann
2021	—	`conf`	High-speed Hardware Accelerator for Trace Decoding in Real-Time Program Monitoring. LASCAS Augusto W. Hoppe, Jürgen Becker, Fernanda Lima Kastensmidt
2021	—	`conf`	Model-based Attack Tree Generation for Cybersecurity Risk-Assessments in Automotive. ISSE Matthias Kern, Bo Liu, Victor Pazmino Betancourt, Jürgen Becker
2021	J	`jnl`	Model-based configuration of access protection units for multicore processors in embedded systems. Microprocess. Microsystems Tobias Dörr, Timo Sandmann, Jürgen Becker
2021	—	`conf`	Moving Target and Implementation Diversity Based Countermeasures Against Side-Channel Attacks. ARC Nadir Khan, Benjamin Hettwer, Jürgen Becker
2021	—	`conf`	Multi-layered NoCs with Adaptive Routing for Mixed Criticality Systems. ARC Nidhi Anantharajaiah, Zhe Zhang, Jürgen Becker
2021	—	`conf`	Neuromorphic Vision mit Spiking Neural Networks zur Sturzerkennung im betreuten Wohnen. GI-Jahrestagung Sven Nitzsche, Brian Pachideh, Victor Pazmino Betancourt, Norbert Link, Christoph Schauer, Lukas Theurer, Valentin Haas, Philipp Marquardt, Sergey Biniaminov, Jürgen Becker
2021	C	`conf`	Template-Driven and Hardware-Centric Cross-Domain E/E Architecture Simulation. RSP Kevin Neubauer, Leonard Masing, Michael Mahl, Jürgen Becker, Max E. Kramer, Clemens Reichmann
2021	C	`conf`	Towards Policy-based Task Self-Reallocation in Dynamic Edge Computing Systems. INDIN Victor Pazmino Betancourt, Bo Liu, Jürgen Becker
2021	—	`conf`	Transparent Near-Memory Computing with a Reconfigurable Processor. ARC Fabian Lesniak, Fabian Kreß, Jürgen Becker
2021	—	`conf`	Ultra-low Power Machinery Fault Detection Using Deep Neural Networks. PKDD/ECML Workshops (1) Sven Nitzsche, Moritz Neher, Stefan von Dosky, Jürgen Becker
2021	J	`jnl`	Utilizing and Extending Trusted Execution Environment in Heterogeneous SoCs for a Pay-Per-Device IP Licensing Scheme. IEEE Trans. Inf. Forensics Secur. Nadir Khan, Sven Nitzsche, Asier Garciandia López, Jürgen Becker
2021	—	`conf`	Virtual Verification of E/E Architectures for Secure Automated Driving Functions. ISSE Kevin Neubauer, Marcel Rumez, Huiying Tremmel, Augusto W. Hoppe, Reiner Kriesten, Philipp Nenninger, Eric Sax, Jürgen Becker
2021	B	`conf`	XANDAR: X-by-Construction Design framework for Engineering Autonomous & Distributed Real-time Embedded Software Systems. FPL Jürgen Becker, Leonard Masing, Tobias Dörr, Florian Schade, Georgios Keramidas, Christos P. Antonopoulos, Michail Mavropoulos, Efstratios Tiganourias, Vasilios I. Kelefouras, Konstantinos Antonopoulos, Nikolaos S. Voros, Umut Durak, Alexander Ahlbrecht, Wanja Zaeske, Christos Panagiotou, Dimitris Karadimas, Nico Adler, Andreas Sailer, Raphael Weber, Thomas Wilhelm, Florian Oszwald, Dominik Reinhardt, Mohamad Chamas, Adnan Bekan, Graham Smethurst, Fahad Siddiqui, Rafiullah Khan, Vahid Garousi, Sakir Sezer, Victor Morales
2020	C	`conf`	A Formal Model for the Automatic Configuration of Access Protection Units in MPSoC-Based Embedded Systems. DSD Tobias Dörr, Timo Sandmann, Jürgen Becker
2020	—	`conf`	A Study of the Impact of Formulation of Cost Function in Task Mapping Problem on NoCs. NorCAS Jessé Barreto de Barros, Nidhi Anantharajaiah, Mauricio Ayala-Rincón, Carlos Humberto Llanos Quintero, Jürgen Becker
2020	C	`conf`	An Approach to Cost-Efficient Fault Tolerance in Inherently Redundant Fail-Operational Systems. DSD Tobias Dörr, Timo Sandmann, Patrick Friederich, Arnd Leitner, Jürgen Becker
2020	—	`conf`	An Architecture-based Modeling Approach Using Data Flows for Zone Concepts in Industry 4.0. ISSE Matthias Kern, Emre Taspolatoglu, Fabian Scheytt, Thomas Glock, Bo Liu, Victor Pazmino Betancourt, Jürgen Becker, Eric Sax
2020	—	`conf`	Designing Universal Logic Module FPGA Architectures for Use With Ambipolar Transistor Technology. FPT Johannes Pfau, Maximilian Reuter, Klaus Hofmann, Jürgen Becker
2020	—	`conf`	Embedded Image Processing the European Way: A new platform for the future automotive market. WF-IoT Tim Hotfilter, Fabian Kempf, Jürgen Becker, Dominik Reinhardt, Imen Baili
2020	—	`conf`	Fine Grained Control Flow Checking with Dedicated FPGA Monitors. SoCC Augusto W. Hoppe, Jürgen Becker, Fernanda Lima Kastensmidt
2020	—	`conf`	Fuzzing Framework for ESP32 Microcontrollers. WIFS Matthias Börsig, Sven Nitzsche, Max Eisele, Roland Gröll, Jürgen Becker, Ingmar Baumgart
2020	A	`conf`	Interference-Aware Memory Allocation for Real-Time Multi-Core Systems. RTAS Simon Reder, Jürgen Becker
2020	—	`conf`	Linking Intrusion Detection System Information and System Model to Redesign Security Architecture. SysCon Victor Pazmino Betancourt, Thomas Glock, Aleksei Kharitonov, Matthias Kern, Bo Liu, Eric Sax, Jürgen Becker
2020	—	`conf`	Model-based Development of a Dynamic Container-Based Edge Computing System. ISSE Victor Pazmino Betancourt, Bo Liu, Jürgen Becker
2020	—	`conf`	Towards Ambipolar Planar Devices: The DeFET Device in Area Constrained XOR Applications. LASCAS Maximilian Reuter, Johannes Pfau, Tillmann A. Krauss, Mahdi Moradinasab, Udo Schwalke, Jürgen Becker, Klaus Hofmann
2020	—	`conf`	Towards an On-Demand Redundancy Concept for Autonomous Vehicle Functions using Microservice Architecture. ISSE Bo Liu, Victor Pazmino Betancourt, Yimeng Zhu, Jürgen Becker
2020	A	`conf`	WCET-aware Code Generation and Communication Optimization for Parallelizing Compilers. DATE Simon Reder, Jürgen Becker
2019	—	`conf`	A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s. SoCC Johannes Pfau, Maximilian Reuter, Tanja Harbaum, Klaus Hofmann, Jürgen Becker
2019	—	`conf`	A Network on Chip Adapter for Real-Time and Safety-Critical Applications. SoCC Fabian Kempf, Nidhi Anantharajaiah, Leonard Masing, Jürgen Becker
2019	C	`conf`	A Secure Framework with Remote Configuration of Intellectual Property. ICISSP Nadir Khan, Sven Nitzsche, Jürgen Becker
2019	J	`jnl`	An Efficient High-Throughput Generic QAM Transmitter with Scalable Spiral FIR Filter. J. Circuits Syst. Comput. Shalina Percy Delicia Figuli, Jürgen Becker
2019	J	`jnl`	Cross-Layer Behavioral Modeling and Simulation of E/E-Architectures using PREEvision and Ptolemy II. Simul. Notes Eur. Harald Bucher, Simon Kamm, Jürgen Becker
2019	—	`conf`	Cross-layer behavioral modeling and simulation of E/E-Architectures using preevision and Ptolemy II. SummerSim Harald Bucher, Jürgen Becker, Simon Kamm
2019	—	`conf`	Dynamic and scalable runtime block-based multicast routing for networks on chips. NoCArc@MICRO Nidhi Anantharajaiah, Fabian Kempf, Leonard Masing, Fabian Marc Lesniak, Jürgen Becker
2019	—	`conf`	From MOSFETs to Ambipolar Transistors: A Static DeFET Inverter Cell for SOI. APCCAS Maximilian Reuter, Tillmann A. Krauss, Mahdi Moradinasab, Johannes Pfau, Udo Schwalke, Jürgen Becker, Klaus Hofmann
2019	—	`conf`	Hybrid Prototyping for Manycore Design and Validation. ARC Leonard Masing, Fabian Lesniak, Jürgen Becker
2019	—	`conf`	Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems. ARC Tobias Dörr, Timo Sandmann, Florian Schade, Falco K. Bapp, Jürgen Becker
2019	—	`conf`	Lina: Timing-Constrained High-Level Synthesis Performance Estimator for Fast DSE. FPT André Bannwart Perina, Jürgen Becker, Vanderlei Bonato
2019	—	`conf`	Model-Driven Design of Tools for Multi-Domain Systems with Loosely Coupled Metamodels. SysCon Bo Liu, Victor Pazmino Betancourt, Thomas Glock, Matthias Kern, Eric Sax, Jürgen Becker
2019	—	`conf`	ProfCounter: Line-Level Cycle Counter for Xilinx OpenCL High-Level Synthesis. ICECS André Bannwart Perina, Jürgen Becker, Vanderlei Bonato
2019	—	`conf`	Reconfigurable Module of Multi-mode AES Cryptographic Algorithms for AP SoCs. NORCAS Arthur Silitonga, Zhou Jiang, Nadir Khan, Jürgen Becker
2019	—	`conf`	Reliable Fail-Operational Automotive E/E-Architectures by Dynamic Redundancy and Reconfiguration. SoCC Florian Oszwald, Philipp Obergfell, Matthias Traub, Jürgen Becker
2019	—	`conf`	Secure Local Configuration of Intellectual Property Without a Trusted Third Party. ARC Nadir Khan, Arthur Silitonga, Brian Pachideh, Sven Nitzsche, Jürgen Becker
2019	J	`jnl`	Worst-Case Execution-Time-Aware Parallelization of Model-Based Avionics Applications. J. Aerosp. Inf. Syst. Simon Reder, Fabian Kempf, Harald Bucher, Jürgen Becker, Panayiotis Alefragis, Nikolaos S. Voros, Stefanos Skalistis, Steven Derrien, Isabelle Puaut, Oliver Oey, Timo Stripf, Christian Ferdinand, Clément David, Peer Ulbig, David Müller, Umut Durak
2018	—	`conf`	A Content - Adapted FPGA Memory Architecture with Pattern Recognition Capability and Interval Compressing Technique. SoCC Tanja Harbaum, Matthias Norbert Balzer, Marc Weber, Jürgen Becker
2018	A	`conf`	A WCET-aware parallel programming model for predictability enhanced multi-core architectures. DATE Simon Reder, Leonard Masing, Harald Bucher, Timon D. ter Braak, Timo Stripf, Jürgen Becker
2018	—	`book`	Advances in Aeronautical Informatics, Technologies Towards Flight 4.0. Advances in Aeronautical Informatics Umut Durak, Jürgen Becker, Sven Hartmann, Nikolaos S. Voros
2018	—	`ch.`	Advances in Avionic Platforms: Multi-core Systems. Advances in Aeronautical Informatics Falco K. Bapp, Jürgen Becker
2018	—	`conf`	Control Flow Analysis for Embedded Multi-core Hybrid Systems. ARC Augusto W. Hoppe, Fernanda Lima Kastensmidt, Jürgen Becker
2018	—	`conf`	Data Readout Triggering for Phase 2 of the Belle II Particle Detector Experiment Based on Neural Networks. SoCC Steffen Baehr, Fabian Kempf, Jürgen Becker
2018	—	`conf`	Dynamic Reconfiguration for Real-Time Automotive Embedded Systems in Fail-Operational Context. IPDPS Workshops Florian Oszwald, Jürgen Becker, Philipp Obergfell, Matthias Traub
2018	—	`conf`	HLS-Based Performance and Resource Optimization of Cryptographic Modules. ISPA/IUCC/BDCloud/SocialCom/SustainCom Arthur Silitonga, Florian Schade, Guanru Jiang, Jürgen Becker
2018	—	`conf`	In-NoC Circuits for Low-Latency Cache Coherence in Distributed Shared-Memory Architectures. MCSoC Leonard Masing, Akshay Srivatsa, Fabian Kreß, Nidhi Anantharajaiah, Andreas Herkersdorf, Jürgen Becker
2018	—	`conf`	Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach. ARC Panayiotis Alefragis, George Theodoridis, Merkourios Katsimpris, Christos Valouxis, Christos Gogos, George Goulas, Nikolaos S. Voros, Simon Reder, Koray Kasnakli, Marcus Bednara, David Müller, Umut Durak, Jürgen Becker
2018	J	`jnl`	OpenCL-based Virtual Prototyping and Simulation of Many-Accelerator Architectures. ACM Trans. Embed. Comput. Syst. Efstathios Sotiriou-Xanthopoulos, Leonard Masing, Sotirios Xydis, Kostas Siozios, Jürgen Becker, Dimitrios Soudris
2018	—	`conf`	RAW 2018 Invited Talks. IPDPS Workshops Jürgen Becker, Viktor K. Prasanna, Markus Weimer, Wayne Luk, Kaveh Aasaraai, Derek Chiou
2018	—	`conf`	Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing Systems. ARC Johannes Pfau, Shalina Percy Delicia Figuli, Steffen Bähr, Jürgen Becker
2018	—	`conf`	The ARAMiS Project Initiative - Multicore Systems in Safety- and Mixed-Critical Applications. ARC Jürgen Becker, Falco K. Bapp
2017	—	`ed.`	30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017 SOCC Massimo Alioto, Hai Helen Li, Jürgen Becker, Ulf Schlichtmann, Ramalingam Sridhar
2017	—	`conf`	A reconfigurable high-speed spiral FIR filter architecture. TSP Shalina Percy Delicia Figuli, Peter Figuli, Jürgen Becker
2017	—	`conf`	Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration. SoCC Tanja Harbaum, Christoph Schade, Marvin Damschen, Carsten Tradowsky, Lars Bauer, Jörg Henkel, Jürgen Becker
2017	J	`jnl`	Efficient task spawning for shared memory and message passing in many-core architectures. J. Syst. Archit. Aurang Zaib, Thomas Wild, Andreas Herkersdorf, Jan Heisswolf, Jürgen Becker, Andreas Weichslgartner, Jürgen Teich
2017	A	`conf`	Energy Efficient Scientific Computing on FPGAs using OpenCL. FPGA Dennis Weller, Fabian Oboril, Dimitar Lukarski, Jürgen Becker, Mehdi Baradaran Tahoori
2017	J	`jnl`	Foreword to the Special Section on Reconfigurable Computing. J. Signal Process. Syst. Steven Derrien, Kubilay Atasu, João M. P. Cardoso, Jürgen Becker
2017	J	`jnl`	Multicore technology in the mobility domains. it Inf. Technol. Jürgen Becker
2017	—	`conf`	Opening remarks. SoCC Jürgen Becker
2017	—	`conf`	Opening remarks. SoCC Jürgen Becker
2017	—	`conf`	Parameter Sensitivity in Virtual FPGA Architectures. ARC Peter Figuli, Weiqiao Ding, Shalina Percy Delicia Figuli, Kostas Siozios, Dimitrios Soudris, Jürgen Becker
2017	A	`conf`	WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach. DATE Steven Derrien, Isabelle Puaut, Panayiotis Alefragis, Marcus Bednara, Harald Bucher, Clément David, Yann Debray, Umut Durak, Imen Fassi, Christian Ferdinand, Damien Hardy, Angeliki Kritikakou, Gerard K. Rauwerda, Simon Reder, Martin Sicks, Timo Stripf, Kim Sunesen, Timon D. ter Braak, Nikolaos S. Voros, Jürgen Becker
2016	Misc	`conf`	A Content Adapted FPGA Memory Architecture with Pattern Recognition Capability for L1 Track Triggering in the LHC Environment. FCCM Tanja Harbaum, Mahmoud Seboui, Matthias Norbert Balzer, Jürgen Becker, Marc Weber
2016	—	`conf`	A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core Systems. ARC Carsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper, Jürgen Becker
2016	—	`conf`	A variable FPGA based generic QAM transmitter with scalable mixed time and frequency domain signal processing. TSP Shalina Percy Delicia Figuli, Alberto Sonnino, Peter Figuli, Jürgen Becker
2016	—	`conf`	Adaptive Bandwidth Router for 3D Network-on-Chips. ARC Stephanie Friederich, Niclas Lehmann, Jürgen Becker
2016	—	`conf`	Adaptive Cache Structures. ARCS Carsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper, Jürgen Becker
2016	—	`conf`	An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures. SAMOS Efstathios Sotiriou-Xanthopoulos, Leonard Masing, Kostas Siozios, George Economakos, Dimitrios Soudris, Jürgen Becker
2016	J	`jnl`	Cloud-based Design and Virtual Prototyping Environment for Embedded Systems. Int. J. Online Eng. Stephan Werner, Andreas Lauber, Martijn Koedam, Jürgen Becker, Eric Sax, Kees Goossens
2016	J	`jnl`	High-Speed Medical Imaging in 3D Ultrasound Computer Tomography. IEEE Trans. Parallel Distributed Syst. Matthias Birk, Ernst Kretzek, Peter Figuli, Marc Weber, Jürgen Becker, Nicole V. Ruiter
2016	—	`conf`	Power Management Controller for Online Power Saving in Network-on-Chips. MCSoC Stephanie Friederich, Marco Neber, Jürgen Becker
2016	—	`conf`	Programmable Logic as Device Virtualization Layer in Heterogeneous Multicore Architectures. ARC Falco K. Bapp, Oliver Sander, Timo Sandmann, Hannes Stoll, Jürgen Becker
2016	J	`jnl`	Providing fault tolerance through invasive computing. it Inf. Technol. Vahid Lari, Andreas Weichslgartner, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Jürgen Teich, Jan Heißwolf, Stephanie Friederich, Jürgen Becker
2016	—	`conf`	Tutorial 2A: 3D integration - challenges and advantages. SoCC Malgorzata Chrzanowska-Jeske, Jürgen Becker
2016	—	`conf`	Tutorial 3A: Bringing cores closer together: The wireless revolution in on-chip communication. SoCC Partha Pande, Jürgen Becker
2015	C	`conf`	A Distributed Simulation Platform Using HLA for Complex Embedded Systems Design. DS-RT Alisson Vasconcelos de Brito, Harald Bucher, Helder F. de A. Oliveira, Luis Feliphe S. Costa, Oliver Sander, Elmar U. K. Melcher, Jürgen Becker
2015	—	`conf`	A Framework for Multi-FPGA Interconnection using Multi Gigabit Transceivers. SBCCI Michael Dreschmann, Jan Heisswolf, Michael Geiger, Manuel Haußecker, Jürgen Becker
2015	—	`conf`	A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware. ARC Peter Figuli, Carsten Tradowsky, Jose Martinez, Harry Sidiropoulos, Kostas Siozios, Holger Stenschke, Dimitrios Soudris, Jürgen Becker
2015	—	`conf`	A V2X message evaluation methodology and cross-domain modelling of safety applications in V2X-enabled E/E-architectures. SimuTools Harald Bucher, Marius-Florian Buciuman, Alexander Klimm, Oliver Sander, Jürgen Becker
2015	—	`conf`	A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU models. SAMOS Efstathios Sotiriou-Xanthopoulos, Shalina Percy Delicia, Peter Figuli, Kostas Siozios, George Economakos, Jürgen Becker
2015	J	`jnl`	Adaptive algorithm and tool flow for accelerating SystemC on many-core architectures. Microprocess. Microsystems Simon Reder, Christoph Roth, Harald Bucher, Oliver Sander, Jürgen Becker
2015	—	`conf`	Design of an embedded UWB hardware platform for navigation in GPS denied environments. SCVT Frank Hartmann, Felix Pistorius, Andreas Lauber, Kai Hildenbrand, Jürgen Becker, Wilhelm Stork
2015	—	`conf`	Designing applications for heterogeneous many-core architectures with the FlexTiles Platform. SAMOS Benedikt Janßen, Fynn Schwiegelshohn, Martijn Koedam, François Duhem, Leonard Masing, Stephan Werner, Christophe Huriaux, Antoine Courtay, Emilie Wheatley, Kees Goossens, Fabrice Lemonnier, Philippe Millet, Jürgen Becker, Olivier Sentieys, Michael Hübner
2015	—	`conf`	Evaluation of analog and digital signal processing on PSoC architecture with DCT as use case: Comparison of an analog and software based implementation of the digital cosine transform on a Programmable System on Chip. DASIP Stephan Werner, Bernhard Stiehle, Jürgen Becker
2015	—	`conf`	Fault-tolerant communication in invasive networks on chip. AHS Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Stephanie Friederich, Leonard Masing, Carsten Stein, Marco Duden, Roman Klopfer, Jürgen Teich, Thomas Wild, Andreas Herkersdorf, Jürgen Becker
2015	—	`conf`	Network Interface with Task Spawning Support for NoC-Based DSM Architectures. ARCS Aurang Zaib, Jan Heißwolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, Andreas Herkersdorf
2015	—	`conf`	On-demand reconfiguration for coprocessors in mixed criticality multicore systems. HPCS Viet Vu Duy, Oliver Sander, Timo Sandmann, Jan Heidelberger, Steffen Baehr, Jürgen Becker
2015	J	`jnl`	Parallelization of genetic algorithms for sorting permutations by reversals over biological data. Int. J. Hybrid Intell. Syst. José Luis Soncco-Álvarez, Gabriel Marchesan Almeida, Jürgen Becker, Mauricio Ayala-Rincón
2015	C	`conf`	Parametric design space exploration for optimizing QAM based high-speed communication. ICCC Shalina Percy Delicia, George Ford, Peter Figuli, Jürgen Becker
2015	C	`conf`	Power Estimation of an ECDSA Core Applied in V2X Scenarios Using Heterogeneous Distributed Simulation. DS-RT Harald Bucher, Alexander Klimm, Oliver Sander, Jürgen Becker
2015	—	`conf`	RAW Introduction and Committees. IPDPS Workshops Jürgen Becker, Ken Eguro, Diana Göhringer, Wayne Luk, Marco D. Santambrogio, Ramachandran Vaidyanathan, Steven J. E. Wilton
2015	B	`conf`	Software-in-the-Loop simulation of embedded control applications based on Virtual Platforms. FPL Stephan Werner, Leonard Masing, Fabian Lesniak, Jürgen Becker
2015	—	`conf`	TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools. ARC Kostas Siozios, Peter Figuli, Harry Sidiropoulos, Carsten Tradowsky, Dionysios Diamantopoulos, Konstantinos Maragos, Shalina Percy Delicia, Dimitrios Soudris, Jürgen Becker
2015	—	`conf`	Virtual prototyping of heterogeneous dynamic platforms using Open Virtual Platforms. SIES Leonard Masing, Stephan Werner, Jürgen Becker
2014	C	`conf`	A Hierarchical Architecture Description for Flexible Multicore System Simulation. ISPA Thomas Bruckschlögl, Oliver Oey, Michael Rückauer, Timo Stripf, Jürgen Becker
2014	J	`jnl`	A comprehensive comparison of GPU- and FPGA-based acceleration of reflection image reconstruction for 3D ultrasound computer tomography. J. Real Time Image Process. Matthias Birk, Michael Zapf, Matthias Norbert Balzer, Nicole V. Ruiter, Jürgen Becker
2014	—	`conf`	A flexible interface architecture for reconfigurable coprocessors in embedded multicore systems using PCIe Single-root I/O virtualization. FPT Oliver Sander, Steffen Baehr, Enno Lübbers, Timo Sandmann, Viet Vu Duy, Jürgen Becker
2014	C	`conf`	Adaptive Algorithm and Tool Flow for Accelerating System C on Many-Core Architectures. DSD Christoph Roth, Simon Reder, Harald Bucher, Oliver Sander, Jürgen Becker
2014	Misc	`conf`	An ultra-high speed OFDMA system for optical access networks. ICNC Michael Dreschmann, Joachim Meyer, Philipp C. Schindler, René Schmogrow, Juerg Leuthold, Wolfgang Freude, Jürgen Becker
2014	—	`conf`	Architectural measures against radiation effects in multicore SoC for safety critical applications. MWSCAS Oliver Sander, Falco Bapp, Timo Sandmann, Viet Vu Duy, Steffen Bähr, Jürgen Becker
2014	A*	`conf`	CAP: Communication Aware Programming. DAC Jan Heisswolf, Aurang Zaib, Andreas Zwinkau, Sebastian Kobbe, Andreas Weichslgartner, Jürgen Teich, Jörg Henkel, Gregor Snelting, Andreas Herkersdorf, Jürgen Becker
2014	—	`conf`	Enabling partial reconfiguration for coprocessors in mixed criticality multicore systems using PCI express single-root I/O virtualization. ReConFig Viet Vu Duy, Oliver Sander, Timo Sandmann, Steffen Bähr, Jan Heidelberger, Jürgen Becker
2014	J	`jnl`	Evaluation of performance and architectural efficiency of FPGAs and GPUs in the 40 and 28 nm generations for algorithms in 3D ultrasound computer tomography. Comput. Electr. Eng. Matthias Birk, Matthias Norbert Balzer, Nicole V. Ruiter, Jürgen Becker
2014	—	`conf`	Flexible real-time transmitter at 10 Gbit/s for SCFDMA PONs focusing on low-cost ONUs. DASIP Lukas Meder, Philipp C. Schindler, Amos Agmon, Maxim Meltsin, Rene Bonk, Joachim Meyer, Michael Dreschmann, Alex Tolmachev, Rolf B. Hilgendorf, Moshe Nazarathy, Shalva Ben-Ezra, Thomas Pfeiffer, Wolfgang Freude, Juerg Leuthold, Christian Koos, Jürgen Becker
2014	J	`jnl`	GPU-based iterative transmission reconstruction in 3D ultrasound computer tomography. J. Parallel Distributed Comput. Matthias Birk, Robin Dapp, Nicole V. Ruiter, Jürgen Becker
2014	A	`conf`	Hardware virtualization support for shared resources in mixed-criticality multicore systems. DATE Oliver Sander, Timo Sandmann, Viet Vu Duy, Steffen Bähr, Falco Bapp, Jürgen Becker, Hans-Ulrich Michel, Dirk Kaule, Daniel Adam, Enno Lübbers, Jürgen Hairbucher, Andre Oliver Richter, Christian Herber, Andreas Herkersdorf
2014	—	`conf`	Hardware/software debugging of large scale many-core architectures. SBCCI Stephanie Friederich, Jan Heisswolf, Jürgen Becker
2014	—	`conf`	Profile-Guided Compilation of Scilab Algorithms for Multiprocessor Systems. ARC Jürgen Becker, Thomas Bruckschlögl, Oliver Oey, Timo Stripf, George Goulas, Nick Raptis, Christos Valouxis, Panayiotis Alefragis, Nikolaos S. Voros, Christos Gogos
2014	—	`conf`	RAW Introduction and Committees. IPDPS Workshops Jürgen Becker, Ramachandran Vaidyanathan, Marco D. Santambrogio, Jim Tørresen, Ron Sass, Philip Heng Wai Leong
2014	C	`conf`	SmartLoCore: A Concept for an Adaptive Power-Aware Localization Processor. PDP Carsten Tradowsky, Tobias Gädeke, Thomas Bruckschlögl, Wilhelm Stork, Klaus D. Müller-Glaser, Jürgen Becker
2014	—	`conf`	The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure. ARCS Workshops Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Martin Karle, Maximilian Singh, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker
2014	—	`conf`	Towards Dynamic Cache and Bandwidth Invasion. ARC Carsten Tradowsky, Martin Schreiber, Malte Vesper, Ivan Domladovec, Maximilian Braun, Hans-Joachim Bungartz, Jürgen Becker
2014	—	`conf`	Ultra-dense, single-wavelength DFT-spread OFDM PON with laserless 1 Gb/s ONU at only 300 MBd per spectral group. ECOC Philipp C. Schindler, Amos Agmon, Stefan Wolf, Rene Bonk, Lukas Meder, Maxim Meltsin, A. Ludwig, Jürgen Becker, Moshe Nazarathy, Shalva Ben-Ezra, Thomas Pfeiffer, Wolfgang Freude, Juerg Leuthold, Christian Koos
2014	—	`conf`	Virtualization Support for FPGA-Based Coprocessors Connected via PCI Express to an Intel Multicore Platform. IPDPS Workshops Viet Vu Duy, Timo Sandmann, Steffen Baehr, Oliver Sander, Jürgen Becker
2013	—	`conf`	A SystemC modeling and simulation methodology for fast and accurate parallel MPSoC simulation. SBCCI Christoph Roth, Harald Bucher, Simon Reder, Florian Buciuman, Oliver Sander, Jürgen Becker
2013	—	`conf`	A flexible implementation of the PSO algorithm for fine- and coarse-grained reconfigurable embedded systems. ReConFig Michael Rückauer, Daniel M. Muñoz, Timo Stripf, Oliver Oey, Carlos H. Llanos, Jürgen Becker
2013	—	`conf`	A novel system on chip for software-defined, high-speed OFDM signal processing. SBCCI Joachim Meyer, Michael Dreschmann, Djorn Karnick, Philipp C. Schindler, Wolfgang Freude, Juerg Leuthold, Jürgen Becker
2013	B	`conf`	A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization. FPL Harry Sidiropoulos, Peter Figuli, Kostas Siozios, Dimitrios Soudris, Jürgen Becker
2013	C	`conf`	AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections. DSD Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, Andreas Herkersdorf
2013	—	`conf`	Addiguration: Exploring configuration behavior of Spartan-3 devices. ReCoSoC Michael Dreschmann, Oliver Sander, Alexander Klimm, Christoph Roth, Jürgen Becker
2013	Misc	`conf`	An FPGA-based multi-core approach for pipelining computing stages. SAC Ali Azarian, João M. P. Cardoso, Stephan Werner, Jürgen Becker
2013	C	`conf`	Coarse-Grain Optimization and Code Generation for Embedded Multicore Systems. DSD George Goulas, Christos Valouxis, Panayiotis Alefragis, Nikolaos S. Voros, Christos Gogos, Oliver Oey, Timo Stripf, Thomas Bruckschlögl, Jürgen Becker, Ali El Moussawi, Maxime Naullet, Tomofumi Yuki
2013	J	`jnl`	Colorless FDMA-PON With Flexible Bandwidth Allocation and Colorless, Low-Speed ONUs [Invited]. JOCN Philipp C. Schindler, René Schmogrow, Michael Dreschmann, Joachim Meyer, Ioannis Tomkos, Josep Prat, Heinz-Georg Krimmel, Thomas Pfeiffer, Pandelis Kourtessis, A. Ludwig, Djorn Karnick, David Hillerkuss, Jürgen Becker, Christian Koos, Wolfgang Freude, Juerg Leuthold
2013	J	`jnl`	Compiling Scilab to high performance embedded multicore systems. Microprocess. Microsystems Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Olivier Sentieys, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Dimitrios Kritharidis, Nikolaos Mitas, Thomas Perschke
2013	C	`conf`	Concurrent Error Detection in Multipliers by Using Reduced Wordlength Multiplication and Logarithms. DSD Alexander Uhl, Jürgen Becker
2013	C	`conf`	Development and Evaluation of Distributed Simulation of Embedded Systems Using Ptolemy and HLA. DS-RT Alisson Vasconcelos de Brito, Angelo V. Negreiros, Christoph Roth, Oliver Sander, Jürgen Becker
2013	—	`conf`	Efficient memory access in 2D Mesh NoC architectures using high bandwidth routers. SBCCI Jan Heisswolf, Simon Bischof, Michael Rückauer, Jürgen Becker
2013	—	`conf`	Flexible WDM-PON with Nyquist-FDM and 31.25 Gbit/s per wavelength channel using colorless, low-speed ONUs. OFC/NFOEC Philipp C. Schindler, René Schmogrow, Michael Dreschmann, Joachim Meyer, David Hillerkuss, Ioannis Tomkos, Josep Prat, Heinz-Georg Krimmel, Thomas Pfeiffer, Pandelis Kourtessis, Jürgen Becker, Christian Koos, Wolfgang Freude, Juerg Leuthold
2013	J	`jnl`	Hardware Support for Authentication in Cyber Physical Systems. it Inf. Technol. Oliver Sander, Alexander Klimm, Jürgen Becker
2013	—	`conf`	Hardware Supported Adaptive Data Collection for Networks on Chip. IPDPS Workshops Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Ralf König, Thomas Wild, Andreas Herkersdorf, Jürgen Teich, Jürgen Becker
2013	A	`conf`	Hybrid interconnect design for heterogeneous hardware accelerators. DATE Cuong Pham-Quoc, Jan Heisswolf, Stephan Werner, Zaid Al-Ars, Jürgen Becker, Koen Bertels
2013	—	`conf`	Improving parallel MPSoC simulation performance by exploiting dynamic routing delay prediction. ReCoSoC Christoph Roth, Harald Bucher, Simon Reder, Oliver Sander, Jürgen Becker
2013	J	`jnl`	JITPR: A framework for supporting fast application's implementation onto FPGAs. ACM Trans. Reconfigurable Technol. Syst. Harry Sidiropoulos, Kostas Siozios, Peter Figuli, Dimitrios Soudris, Michael Hübner, Jürgen Becker
2013	—	`conf`	LImbiC: An adaptable architecture description language model for developing an application-specific image processor. ISVLSI Carsten Tradowsky, Tanja Harbaum, Shaver Deyerle, Jürgen Becker
2013	J	`jnl`	MORPHEUS: A heterogeneous dynamically reconfigurable platform for designing highly complex embedded systems. ACM Trans. Embed. Comput. Syst. Nikolaos S. Voros, Michael Hübner, Jürgen Becker, Matthias Kühnle, Florian Thoma, Arnaud Grasset, Paul Brelet, Philippe Bonnot, Fabio Campi, Eberhard Schüler, Henning Sahlbach, Sean Whitty, Rolf Ernst, Enrico Billich, Claudia Tischendorf, Ulrich Heinkel, Frank Ieromnimon, Dimitrios Kritharidis, Axel Schneider, Joachim Knäblein, Wolfram Putzke-Röming
2013	—	`conf`	Parallelization and virtualization of genetic algorithms for sorting permutations by reversals. NaBIC José Luis Soncco-Álvarez, Gabriel Marchesan Almeida, Jürgen Becker, Mauricio Ayala-Rincón
2013	J	`jnl`	Providing multiple hard latency and throughput guarantees for packet switching networks on chip. Comput. Electr. Eng. Jan Heisswolf, Ralf König, Martin Kupper, Jürgen Becker
2013	J	`jnl`	QUKU: A dual-layer reconfigurable architecture. ACM Trans. Embed. Comput. Syst. Neil W. Bergmann, Sunil Shukla, Jürgen Becker
2013	—	`conf`	RAW Introduction. IPDPS Workshops Jürgen Becker, Ramachandran Vaidyanathan, Peter Athanas, Marco D. Santambrogio, René Cumplido, Oliver Sander
2013	J	`jnl`	Reliable and adaptive network-on-chip architectures for cyber physical systems. ACM Trans. Embed. Comput. Syst. Diana Göhringer, Lukas Meder, Oliver Oey, Jürgen Becker
2013	—	`conf`	Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocation. ReConFig Jan Heisswolf, Maximilian Singh, Martin Kupper, Ralf König, Jürgen Becker
2013	J	`jnl`	Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011). Int. J. Reconfigurable Comput. René Cumplido, Peter Athanas, Jürgen Becker
2013	J	`jnl`	Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011). Int. J. Reconfigurable Comput. Massimo Conti, Elmar U. K. Melcher, Jürgen Becker, Alisson Vasconcelos de Brito, Oliver Sander
2013	—	`conf`	Simplify: A Framework for Enabling Fast Functional/Behavioral Validation of Multiprocessor Architectures in the Cloud. IPDPS Workshops Gabriel Marchesan Almeida, Oliver Bellaver Longhi, Thomas Bruckschlögl, Michael Hübner, Fabiano Hessel, Jürgen Becker
2013	—	`conf`	ViSA: A highly efficient slot architecture enabling multi-objective ASIP cores. ISSoC Peter Figuli, Carsten Tradowsky, Nadine Gaertner, Jürgen Becker
2013	J	`jnl`	Virtual networks - distributed communication resource management. ACM Trans. Reconfigurable Technol. Syst. Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker
2012	—	`conf`	A Compilation- and Simulation-Oriented Architecture Description Language for Multicore Systems. CSE Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Ralf König, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Jordy Potman, Kim Sunesen, Steven Derrien, Olivier Sentieys, Jürgen Becker
2012	—	`conf`	A Compiler Back-End for Reconfigurable, Mixed-ISA Processors with Clustered Register Files. IPDPS Workshops Timo Stripf, Ralf König, Patrick Rieder, Jürgen Becker
2012	—	`conf`	A Framework for exploration of parallel SystemC simulation on the single-chip cloud computer. SimuTools Christoph Roth, Simon Reder, Oliver Sander, Michael Hübner, Jürgen Becker
2012	C	`conf`	A Scalable NoC Router Design Providing QoS Support Using Weighted Round Robin Scheduling. ISPA Jan Heisswolf, Ralf König, Jürgen Becker
2012	A	`conf`	A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture. DATE Timo Stripf, Ralf König, Jürgen Becker
2012	—	`conf`	A flexible approach for compiling scilab to reconfigurable multi-core embedded systems. ReCoSoC Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Ralf König, Michael Hübner, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Dimitrios Kritharidis, Nikolaos Mitas, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Daniel Ménard, Olivier Sentieys, Diana Göhringer, Thomas Perschke
2012	J	`jnl`	Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration. Int. J. Reconfigurable Comput. Diana Göhringer, Lukas Meder, Stephan Werner, Oliver Oey, Jürgen Becker, Michael Hübner
2012	—	`conf`	Adaptive processor architecture - invited paper. ICSAMOS Michael Hübner, Diana Göhringer, Carsten Tradowsky, Jörg Henkel, Jürgen Becker
2012	—	`conf`	Asynchronous parallel MPSoC simulation on the Single-Chip Cloud Computer. ISSoC Christoph Roth, Simon Reder, Gokhan Erdogan, Oliver Sander, Gabriel Marchesan Almeida, Harald Bucher, Jürgen Becker
2012	—	`conf`	Comparison of processing performance and architectural efficiency metrics for FPGAs and GPUs in 3D Ultrasound Computer Tomography. ReConFig Matthias Birk, Matthias Norbert Balzer, Nicole V. Ruiter, Jürgen Becker
2012	—	`conf`	Determination of on-chip temperature gradients on reconfigurable hardware. ReConFig Carsten Tradowsky, Enrique Cordero, Thorsten Deuser, Michael Hübner, Jürgen Becker
2012	J	`jnl`	Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels. Int. J. Reconfigurable Comput. Christoph Roth, Joachim Meyer, Michael Rückauer, Oliver Sander, Jürgen Becker
2012	J	`jnl`	Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices. Int. J. Reconfigurable Comput. Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker
2012	—	`conf`	FPGA system-on-chip solution for a field oriented hybrid stepper motor control. SSD Nadine Dahm, Michael Hübner, Jürgen Becker
2012	C	`conf`	Framework for dynamic verification of multi-domain virtual platforms in industrial automation. INDIN Francisco Mendoza, Joris Pascal, Philipp Nenninger, Jürgen Becker
2012	C	`conf`	From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach. DSD Jürgen Becker, Timo Stripf, Oliver Oey, Michael Hübner, Steven Derrien, Daniel Ménard, Olivier Sentieys, Gerard K. Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Kostas Masselos, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Dimitrios Kritharidis, Nikolaos Mitas, Diana Göhringer
2012	—	`conf`	From Scilab to multicore embedded systems: Algorithms and methodologies. ICSAMOS George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Göhringer, Steven Derrien, Daniel Ménard, Olivier Sentieys, Michael Hübner, Timo Stripf, Oliver Oey, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas
2012	—	`conf`	Hardware / Software Virtualization for the Reconfigurable Multicore Platform. CSE Max Ferger, Muhammed Al Kadi, Michael Hübner, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Gabriel Marchesan Almeida, José Rodrigo Azambuja, Jürgen Becker
2012	—	`conf`	Hardware prototyping of novel invasive multicore architectures. ASP-DAC Jürgen Becker, Stephanie Friederich, Jan Heisswolf, Ralf König, David May
2012	—	`conf`	Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS. IPDPS Workshops Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker
2012	J	`jnl`	HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture. Int. J. Reconfigurable Comput. Alexander Thomas, Michael Rückauer, Jürgen Becker
2012	—	`conf`	LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture. SIES Carsten Tradowsky, Florian Thoma, Michael Hübner, Jürgen Becker
2012	J	`jnl`	Modeling and Implementation of a Power Estimation Methodology for SystemC. Int. J. Reconfigurable Comput. Matthias Kühnle, André Wagner, Alisson Vasconcelos de Brito, Jürgen Becker
2012	—	`conf`	On Dynamic Run-time Processor Pipeline Reconfiguration. IPDPS Workshops Carsten Tradowsky, Florian Thoma, Michael Hübner, Jürgen Becker
2012	A	`conf`	On demand dependent deactivation of automotive ECUs. DATE Christoph Schmutzler, Martin Simons, Jürgen Becker
2012	—	`conf`	RAW Introduction. IPDPS Workshops Jürgen Becker, Jinian Bian, Christophe Bobda, René Cumplido, Michael Hübner
2012	—	`conf`	Realtime PCI Express monitoring for self adaptive reconfigurable systems. SSD Michael Rückauer, Joachim Meyer, Thorsten Schubert, Michael Hübner, Dieter Scheurer, Jürgen Becker
2012	—	`conf`	Scalable Problem-Oriented Approach for Dynamic Verification of Embedded Systems. CESCIT Francisco Mendoza, Philipp Nenninger, Markus Ruppert, Jürgen Becker
2012	J	`jnl`	Single-Laser 325 Tbit/s Nyquist WDM Transmission. JOCN David Hillerkuss, René Schmogrow, Matthias Meyer, Stefan Wolf, Meinert Jordan, Philipp Kleinow, Nicole Lindenmann, Philipp C. Schindler, Argishti Melikyan, Xin Yang, Shalva Ben-Ezra, Bernd Nebendahl, Michael Dreschmann, Joachim Meyer, Francesca Parmigiani, Periklis Petropoulos, Bojan Resan, Andreas Oehler, Kurt Weingarten, Lars Altenhain, Tobias Ellermeyer, Michael Möller, Michael Hübner, Jürgen Becker, Christian Koos, Wolfgang Freude, Juerg Leuthold
2012	J	`jnl`	Single-laser 32.5 Tbit/s Nyquist WDM transmission CoRR David Hillerkuss, René Schmogrow, Matthias Meyer, Stefan Wolf, Meinert Jordan, Philipp Kleinow, Nicole Lindenmann, Philipp C. Schindler, Argishti Melikyan, Xin Yang, Shalva Ben-Ezra, Bernd Nebendahl, Michael Dreschmann, Joachim Meyer, Francesca Parmigiani, Periklis Petropoulos, Bojan Resan, Andreas Oehler, Kurt Weingarten, Lars Altenhain, Tobias Ellermeyer, Matthias Moeller, Michael Hübner, Jürgen Becker, Christian Koos, Wolfgang Freude, Juerg Leuthold
2012	Misc	`conf`	Time and frequency synchronization for ultra-high speed OFDM systems. ICNC Michael Dreschmann, Joachim Meyer, Michael Hübner, René Schmogrow, David Hillerkuss, Jürgen Becker, Juerg Leuthold, Wolfgang Freude
2012	—	`conf`	Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures. ICSAMOS Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hübner, Jürgen Becker, Sébastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire
2012	—	`conf`	Virtualization of heterogeneous and adaptive multi-core/multi-board systems. DASIP Oliver Oey, Stephan Werner, Diana Göhringer, Andreas Stuckert, Jürgen Becker, Michael Hübner
2012	A	`conf`	Virtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems. DATE Stephan Werner, Oliver Oey, Diana Göhringer, Michael Hübner, Jürgen Becker
2012	—	`conf`	Xilinx tools facilitate development of FPGA applications for IEC61508. AHS Giulio Corradi, Romuald Girardey, Jürgen Becker
2011	—	`ed.`	2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011 ReConFig Peter M. Athanas, Jürgen Becker, René Cumplido
2011	—	`ed.`	24th Symposium on Integrated Circuits and Systems Design, SBCCI '11, João Pessoa, Brazil, August 30 - September 2, 2011 SBCCI Antonio Carlos Cavalcanti, Elmar U. K. Melcher, Jürgen Becker
2011	—	`ed.`	3rd Many-core Applications Research Community (MARC) Symposium. Proceedings of the 3rd MARC Symposium, Ettlingen, Germany, July 5-6, 2011 MARC Symposium Diana Göhringer, Michael Hübner, Jürgen Becker
2011	C	`conf`	A FPGA based fast runtime reconfigurable real-time Multi-Object-Tracker. ISCAS Matthias Rümmele-Werner, Thomas Perschke, Lars Braun, Michael Hübner, Jürgen Becker
2011	—	`conf`	A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture. IPDPS Workshops Michael Hübner, Peter Figuli, Romuald Girardey, Dimitrios Soudris, Kostas Siozios, Jürgen Becker
2011	—	`conf`	A Scalable Microarchitecture Design that Enables Dynamic Code Execution for Variable-Issue Clustered Processors. IPDPS Workshops Ralf König, Timo Stripf, Jan Heisswolf, Jürgen Becker
2011	J	`jnl`	A Security Scheme for Dependable Key Insertion in Mobile Embedded Devices. Int. J. Reconfigurable Comput. Alexander Klimm, Benjamin Glas, Matthias Wachs, Sebastian Vogel, Klaus D. Müller-Glaser, Jürgen Becker
2011	—	`conf`	A heterogeneous SoC architecture with embedded virtual FPGA cores and runtime Core Fusion. AHS Peter Figuli, Michael Hübner, Romuald Girardey, Falco Bapp, Thomas Bruckschlögl, Florian Thoma, Jörg Henkel, Jürgen Becker
2011	—	`conf`	A novel ADL-based compiler-centric software framework for reconfigurable mixed-ISA processors. ICSAMOS Timo Stripf, Ralf König, Jürgen Becker
2011	—	`conf`	A statistical power estimation methodology embedded in a SystemC code translator. SBCCI Matthias Kühnle, André Wagner, Jürgen Becker
2011	—	`conf`	A study on fine granular fault tolerance methodologies for FPGAs. ReCoSoC Mahtab Niknahad, Oliver Sander, Jürgen Becker
2011	—	`conf`	Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing. DASIP Matthias Birk, Alexander Guth, Michael Zapf, Matthias Norbert Balzer, Nicole V. Ruiter, Michael Hübner, Jürgen Becker
2011	—	`conf`	Adaptive Multi-client Network-on-Chip Memory. ReConFig Diana Göhringer, Lukas Meder, Michael Hübner, Jürgen Becker
2011	—	`ch.`	Adaptive Multiprocessor System-on-Chip Architecture: New Degrees of Freedom in System Design and Runtime Support. Multiprocessor System-on-Chip Diana Göhringer, Michael Hübner, Jürgen Becker
2011	—	`conf`	An approach for power and performance evaluation of reconfigurable SoC at mixed abstraction levels. ReCoSoC Matthias Kühnle, Alisson Vasconcelos de Brito, Christoph Roth, Matthias Krüsselin, Jürgen Becker
2011	C	`conf`	An automated approach to SystemC/Simulink co-simulation. International Symposium on Rapid System Prototyping Francisco Mendoza, Christian Köllner, Jürgen Becker, Klaus D. Müller-Glaser
2011	—	`conf`	Ansätze zur Integration von energieeffizienten Intelligenten Kommunikationskontrollern für FlexRay in Autosar. GI-Jahrestagung Christoph Schmutzler, Andreas Krüger, Martin Simons, Jürgen Becker
2011	—	`conf`	Approach of an FPGA based adaptive stepper motor control system. ReCoSoC Nadine Dahm, Michael Hübner, Jürgen Becker
2011	—	`conf`	Architecture design space exploration of run-time scalable issue-width processors. ICSAMOS Ralf König, Timo Stripf, Jan Heisswolf, Jürgen Becker
2011	—	`conf`	Development of a method for image-based motion estimation of a VTOL-MAV on FPGA. DASIP Natalie Frietsch, I. Pashkovskiy, Gert F. Trommer, Lars Braun, Matthias Birk, Michael Hübner, Jürgen Becker
2011	C	`conf`	Digital On-demand Computing Organism - Interaction between Monitoring and Middleware. ISORC Alexander von Renteln, Uwe Brinkschulte, David Kramer, Wolfgang Karl, Christian Schuck, Jürgen Becker
2011	—	`ch.`	DodOrg - A Self-adaptive Organic Many-core Architecture. Organic Computing Thomas Ebi, David Kramer, Christian Schuck, Alexander von Renteln, Jürgen Becker, Uwe Brinkschulte, Jörg Henkel, Wolfgang Karl
2011	—	`conf`	Dynamic Processor Reconfiguration. ReConFig Michael Hübner, Carsten Tradowsky, Diana Göhringer, Lars Braun, Florian Thoma, Jörg Henkel, Jürgen Becker
2011	B	`conf`	Embedded Systems Start-Up under Timing Constraints on Modern FPGAs. FPL Joachim Meyer, Juanjo Noguera, Michael Hübner, Rodney Stewart, Jürgen Becker
2011	J	`jnl`	Evaluation of the Reconfiguration of the Data Acquisition System for 3D USCT. Int. J. Reconfigurable Comput. Matthias Birk, Clemens Hagner, Matthias Norbert Balzer, Nicole V. Ruiter, Michael Hübner, Jürgen Becker
2011	J	`jnl`	Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems. Int. J. Reconfigurable Comput. Diana Göhringer, Jonathan Obie, André L. S. Braga, Michael Hübner, Carlos H. Llanos, Jürgen Becker
2011	A	`conf`	Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration. DATE Joachim Meyer, Juanjo Noguera, Michael Hübner, Lars Braun, Oliver Sander, R. M. Gil, Rodney Stewart, Jürgen Becker
2011	—	`conf`	Flexible and efficient co-simulation of networked embedded devices. SBCCI Christoph Roth, Oliver Sander, Jürgen Becker
2011	—	`conf`	HLA-based simulation environment for distributed SystemC simulation. SimuTools Christoph Roth, Oliver Sander, Matthias Kühnle, Jürgen Becker
2011	—	`conf`	Heterogeneous and runtime parameterizable Star-Wheels Network-on-Chip. ICSAMOS Diana Göhringer, Oliver Oey, Michael Hübner, Jürgen Becker
2011	—	`conf`	HoneyComb: A multi-grained dynamically reconfigurable runtime adaptive hardware architecture. SoCC Alexander Thomas, Michael Rückauer, Jürgen Becker
2011	—	`conf`	HoneyComb: an application-driven online adaptive reconfigurable hardware architecture. SBCCI Alexander Thomas, Michael Rückauer, Jürgen Becker
2011	—	`conf`	Hyperelliptic Curve Cryptoarchitecture for Fast Execution of Schnorr and Okamoto Authentication Protocols. IPDPS Workshops Alexander Klimm, Sebastian Vogel, Jürgen Becker
2011	—	`conf`	Increasing energy efficiency of automotive E/E-architectures with Intelligent Communication Controllers for FlexRay. SoC Christoph Schmutzler, Abdallah Lakhtel, Martin Simons, Jürgen Becker
2011	—	`conf`	Modular Framework for Multi-level Multi-device MPSoC Simulation. IPDPS Workshops Christoph Roth, Gabriel Marchesan Almeida, Oliver Sander, Luciano Ost, Nicolas Hebert, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Jürgen Becker
2011	—	`book`	Multiprocessor System-on-Chip - Hardware Design and Tool Integration. Multiprocessor System-on-Chip Michael Hübner, Jürgen Becker
2011	—	`conf`	Online Routing of FPGA Clock Networks for Module Relocation in Partial Reconfigurable Multi Clock Designs. IPDPS Workshops Christian Schuck, Bastian Haetzer, Michael Hübner, Jürgen Becker
2011	J	`jnl`	Operating System for Runtime Reconfigurable Multiprocessor Systems. Int. J. Reconfigurable Comput. Diana Göhringer, Michael Hübner, Etienne Nguepi Zeutebouo, Jürgen Becker
2011	—	`conf`	Power and performance optimization through MPI supported dynamic voltage and frequency scaling. MARC Symposium Florian Thoma, Michael Hübner, Diana Göhringer, Hasan Ümitcan Yilmaz, Jürgen Becker
2011	J	`jnl`	Prime Field ECDSA Signature Processing for Reconfigurable Embedded Systems. Int. J. Reconfigurable Comput. Benjamin Glas, Oliver Sander, Vitali Stuckert, Klaus D. Müller-Glaser, Jürgen Becker
2011	B	`conf`	RAMPSoCVM: Runtime Support and Hardware Virtualization for a Runtime Adaptive MPSoC. FPL Diana Göhringer, Stephan Werner, Michael Hübner, Jürgen Becker
2011	—	`conf`	RAW Introduction. IPDPS Workshops Jürgen Becker, Pascal Benoit, René Cumplido
2011	J	`jnl`	Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs. Int. J. Reconfigurable Comput. Christian Schuck, Bastian Haetzer, Jürgen Becker
2011	Misc	`conf`	Run-Time Resource Allocation for Simultaneous Multi-tasking in Multi-core Reconfigurable Processors. FCCM Waheed Ahmed, Muhammad Shafique, Lars Bauer, Manuel Hammerich, Jörg Henkel, Jürgen Becker
2011	—	`conf`	Run-time resource instantiation for fault tolerance in FPGAs. AHS Monica Magalhães Pereira, Lars Braun, Michael Hübner, Jürgen Becker, Luigi Carro
2011	J	`jnl`	Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010). Int. J. Reconfigurable Comput. Aravind Dasu, João M. P. Cardoso, Eli Bozorgzadeh, Jürgen Becker
2011	J	`jnl`	Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC' 2010). Int. J. Reconfigurable Comput. Michael Hübner, Jürgen Becker, Loïc Lagadec, Gilles Sassatelli
2011	—	`conf`	The Study of a Dynamic Reconfiguration Manager for Systems-on-Chip. ISVLSI Matthias Kühnle, Alisson Vasconcelos de Brito, Christoph Roth, Konstantinos Dagas, Jürgen Becker
2011	—	`conf`	Using dynamic partial reconfiguration to detect sees in microprocessors through non-intrusive hybrid technique. SBCCI José Rodrigo Azambuja, Samuel Pagliarini, Maurício Altieri, Fernanda Lima Kastensmidt, Michael Hübner, Jürgen Becker
2011	C	`ed.`	VLSI-SoC: Technologies for Systems Integration - 17th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2009, Florianópolis, Brazil, October 12-14, 2009, Revised Selected Papers VLSI-SoC Jürgen Becker, Marcelo O. Johann, Ricardo Reis
2010	—	`conf`	10281 Abstracts Collection - Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures Peter M. Athanas, Jürgen Becker, Jürgen Teich, Ingrid Verbauwhede
2010	—	`conf`	10281 Summary - Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures Peter M. Athanas, Jürgen Becker, Jürgen Teich, Ingrid Verbauwhede
2010	Misc	`conf`	A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip. FCCM Diana Göhringer, Michael Hübner, Michael Benz, Jürgen Becker
2010	—	`conf`	A Secure Keyflashing Framework for Access Systems in Highly Mobile Devices. ReCoSoC Alexander Klimm, Benjamin Glas, Matthias Wachs, Jürgen Becker, Klaus D. Müller-Glaser
2010	—	`conf`	A flexible integrated cryptoprocessor for authentication protocols based on hyperelliptic curve cryptography. SoC Alexander Klimm, Matthias Haas, Oliver Sander, Jürgen Becker
2010	A	`conf`	A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only). FPGA Diana Göhringer, Michael Hübner, Michael Benz, Jürgen Becker
2010	—	`ch.`	Adaptive Runtime System with Intelligent Allocation of Dynamically Reconfigurable Function Model and Optimized Interface Topologies. Dynamically Reconfigurable Systems Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Michael Ullmann, Klaus D. Müller-Glaser, Jürgen Becker
2010	—	`conf`	CAP-OS: Operating system for runtime scheduling, task mapping and resource management on reconfigurable multiprocessor architectures. IPDPS Workshops Diana Göhringer, Michael Hübner, Etienne Nguepi Zeutebouo, Jürgen Becker
2010	J	`jnl`	Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems. ACM Trans. Reconfigurable Technol. Syst. Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker
2010	—	`ch.`	Development and Synthesis of Adaptive Multi-grained Reconfigurable Hardware Architecture for Dynamic Function Patterns. Dynamically Reconfigurable Systems Alexander Thomas, Jürgen Becker
2010	—	`conf`	Dynamic Online Reconfiguration of Digital Clock Managers on Xilinx Virtex-II/ Virtex II-Pro FPGAs: A Case Study of Distributed Power Management. ReCoSoC Christian Schuck, Bastian Haetzer, Jürgen Becker
2010	—	`ed.`	Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010 Dynamically Reconfigurable Architectures Peter M. Athanas, Jürgen Becker, Jürgen Teich, Ingrid Verbauwhede
2010	—	`conf`	ECDSA Signature Processing over Prime Fields for Reconfigurable Embedded Systems. ReCoSoC Benjamin Glas, Oliver Sander, Vitali Stuckert, Klaus D. Müller-Glaser, Jürgen Becker
2010	—	`conf`	FPGA Startup Through Sequential Partial and Dynamic Reconfiguration. ISVLSI (Selected papers) Joachim Meyer, Michael Hübner, Lars Braun, Oliver Sander, Juanjo Noguera, Rodney Stewart, Jürgen Becker
2010	—	`conf`	FPGA-Based Runtime Adaptive Multiprocessor Approach for Embedded High Performance Computing Applications. ISVLSI Diana Göhringer, Jürgen Becker
2010	—	`conf`	Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration. ISVLSI Michael Hübner, Joachim Meyer, Oliver Sander, Lars Braun, Jürgen Becker, Juanjo Noguera, Rodney Stewart
2010	—	`conf`	Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs. IPDPS Workshops Michael Hübner, Diana Göhringer, Juanjo Noguera, Jürgen Becker
2010	—	`conf`	First Evaluation of FPGA Reconfiguration for 3D Ultrasound Computer Tomography. ReCoSoC Matthias Birk, Clemens Hagner, Matthias Norbert Balzer, Nicole V. Ruiter, Michael Hübner, Jürgen Becker
2010	J	`jnl`	Guest Editorial ARC 2009. ACM Trans. Reconfigurable Technol. Syst. Roger F. Woods, Jürgen Becker, Peter Athanas, Fearghal Morgan
2010	—	`conf`	High performance reconfigurable multi-processor-based computing on FPGAs. IPDPS Workshops Diana Göhringer, Jürgen Becker
2010	—	`conf`	ISRC: a runtime system for heterogeneous reconfigurable architectures. ReCoSoC Florian Thoma, Jürgen Becker
2010	—	`conf`	Impact of Task Distribution, Processor Configurations and Dynamic Clock Frequency Scaling on the Power Consumption of FPGA-based Multiprocessors. ReCoSoC Diana Goehringer, Jonathan Obie, Michael Hübner, Jürgen Becker
2010	—	`conf`	Intrinsic Identification of Xilinx Virtex-5 FPGA Devices Using Uninitialized Parts of Configuration Memory Space. ReConFig Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker
2010	A	`conf`	KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture. DATE Ralf König, Lars Bauer, Timo Stripf, Muhammad Shafique, Waheed Ahmed, Jürgen Becker, Jörg Henkel
2010	—	`conf`	Message Passing Interface support for the runtime adaptive multi-processor system-on-chip RAMPSoC. ICSAMOS Diana Göhringer, Michael Hübner, Laure Hugot-Derville, Jürgen Becker
2010	—	`conf`	Mixed-Signal Diverse Redundant System for Safety Critical Applications in FPGA. ISVLSI Romuald Girardey, Michael Hübner, Jürgen Becker
2010	—	`conf`	New Dimensions in Design Space and Runtime Adaptivity for Multiprocessor Systems Through Dynamic and Partial Reconfiguration: The RAMPSoC Approach. ISVLSI (Selected papers) Diana Göhringer, Jürgen Becker
2010	—	`conf`	Performance, accuracy, power consumption and resource utilization analysis for hardware / software realized Artificial Neural Networks. BIC-TA André L. S. Braga, Carlos H. Llanos, Diana Göhringer, Jonathan Obie, Jürgen Becker, Michael Hübner
2010	—	`ed.`	Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, ReCoSoC 2010, Karlsruhe, Germany, May 17-19, 2010 ReCoSoC Michael Hübner, Loïc Lagadec, Oliver Sander, Jürgen Becker
2010	—	`ed.`	ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 13-15 December 2010, Proceedings ReConFig Viktor K. Prasanna, Jürgen Becker, René Cumplido
2010	B	`conf`	Reconfigurable Hardware for Power-over-Fiber Applications. FPL Michael Dreschmann, Michael Hübner, Moritz Röger, Oliver Sander, Christos Klamouris, Jürgen Becker, Wolfgang Freude, Juerg Leuthold
2010	—	`conf`	Reliability Analysis and Improvement in Nano Scale Design. ISVLSI Mahtab Niknahad, Michael Hübner, Jürgen Becker
2010	—	`conf`	Safety Aware Place and Route for On-Chip Redundancy in Safety Critical Applications. ISVLSI Romuald Girardey, Michael Hübner, Jürgen Becker
2010	A	`conf`	Scenario extraction for a refined timing-analysis of automotive network topologies. DATE Matthias Traub, Thilo Streichert, Oleg Krasovytskyy, Jürgen Becker
2010	—	`conf`	Two Dimensional Dynamic Multigrained Reconfigurable Hardware. ISVLSI (Selected papers) Lars Braun, Jürgen Becker
2010	—	`conf`	Two-Dimensional Dynamic Multigrained Reconfigurable Hardware. ISVLSI Lars Braun, Jürgen Becker
2010	—	`conf`	Welcome message. IPDPS Workshops Jürgen Becker, Eli Bozorgzadeh, João M. P. Cardoso, Aravind Dasu
2009	A	`conf`	A MicroBlaze specific co-processor for real-time hyperelliptic curve cryptography on Xilinx FPGAs. IPDPS Alexander Klimm, Oliver Sander, Jürgen Becker
2009	J	`jnl`	A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip. Int. J. Reconfigurable Comput. Diana Göhringer, Thomas Perschke, Michael Hübner, Jürgen Becker
2009	—	`conf`	A multi-core signal processor for heterogeneous reconfigurable computing. SoC Davide Rossi, Fabio Campi, Antonio Deledda, Claudio Mucci, Stefano Pucillo, Sean Whitty, Rolf Ernst, Stéphane Chevobbe, Stéphane Guyetant, Matthias Kühnle, Michael Hübner, Jürgen Becker, Wolfram Putzke-Röming
2009	—	`conf`	Adaptive Multicore Systems-on-Chip (MSoC) - Design and Computing in the Nano Era. ERSA Jürgen Becker
2009	J	`jnl`	Adaptive real-time image processing exploiting two dimensional reconfigurable architecture. J. Real Time Image Process. Lars Braun, Diana Göhringer, Thomas Perschke, Volker Schatz, Michael Hübner, Jürgen Becker
2009	J	`jnl`	An Interface for a Decentralized 2D Reconfiguration on Xilinx Virtex-FPGAs for Organic Computing. Int. J. Reconfigurable Comput. Christian Schuck, Bastian Haetzer, Jürgen Becker
2009	—	`conf`	Car-to-Car Communication Security on Reconfigurable Hardware. VTC Spring Benjamin Glas, Oliver Sander, Vitali Stuckert, Klaus D. Müller-Glaser, Jürgen Becker
2009	C	`conf`	Configuration Measurement for FPGA-based Trusted Platforms. IEEE International Workshop on Rapid System Prototyping Benjamin Glas, Alexander Klimm, Klaus D. Müller-Glaser, Jürgen Becker
2009	—	`conf`	Design of a Vehicle-to-Vehicle communication system on reconfigurable hardware. FPT Oliver Sander, Benjamin Glas, Christoph Roth, Jürgen Becker, Klaus D. Müller-Glaser
2009	J	`jnl`	Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems. Microprocess. Microsystems Katarina Paulsson, Michael Hübner, Jürgen Becker
2009	B	`conf`	Dynamic reconfigurable mixed-signal architecture for safety critical applications. FPL Romuald Girardey, Michael Hübner, Jürgen Becker
2009	—	`conf`	FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing. ARC Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker
2009	—	`conf`	Method for improving performance in online routing of reconfigurable nano architectures. SoCC Mahtab Niknahad, Michael Hübner, Jürgen Becker
2009	A	`conf`	Priority-based packet communication on a bus-shaped structure for FPGA-systems. DATE Oliver Sander, Benjamin Glas, Christoph Roth, Jürgen Becker, Klaus D. Müller-Glaser
2009	—	`conf`	RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip. SoC Fabio Campi, Ralf König, Michael Dreschmann, M. Neukirchner, Damien Picard, M. Jüttner, Eberhard Schüler, Antonio Deledda, Davide Rossi, Alberto Pasini, Michael Hübner, Jürgen Becker, Roberto Guerrieri
2009	—	`ed.`	Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings ARC Jürgen Becker, Roger F. Woods, Peter M. Athanas, Fearghal Morgan
2009	B	`conf`	Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol. FPL Diana Göhringer, Bin Liu, Michael Hübner, Jürgen Becker
2009	—	`conf`	System concept for an FPGA based real-time capable automotive ECU simulation system. SBCCI Oliver Sander, Christoph Roth, Vitali Stuckert, Jürgen Becker
2009	C	`conf`	Testing of an FPGA Based C2X-Communication Prototype with a Model Based Traffic Generation. IEEE International Workshop on Rapid System Prototyping Oliver Sander, Benjamin Glas, Christoph Roth, Jürgen Becker, Klaus D. Müller-Glaser
2008	—	`conf`	A Hardware/Software Codesign of a Co-processor for Real-Time Hyperelliptic Curve Cryptography on a Spartan3 FPGA. ARCS Alexander Klimm, Oliver Sander, Jürgen Becker, Sylvain Subileau
2008	A	`conf`	A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms. DATE Ralf König, Timo Stripf, Jürgen Becker
2008	C	`conf`	A Prototype of Trusted Platform Functionality on Reconfigurable Hardware for Bitstream Updates. IEEE International Workshop on Rapid System Prototyping Benjamin Glas, Alexander Klimm, David Schwab, Klaus D. Müller-Glaser, Jürgen Becker
2008	A	`conf`	A System Architecture for Reconfigurable Trusted Platforms. DATE Benjamin Glas, Alexander Klimm, Oliver Sander, Klaus D. Müller-Glaser, Jürgen Becker
2008	—	`conf`	A Web Server Based Edge Detector Implementation in FPGA. ISVLSI Sunil Shukla, Neil W. Bergmann, Jürgen Becker
2008	A	`conf`	A framework for dynamic 2D placement on FPGAs. IPDPS Christian Schuck, Matthias Kühnle, Michael Hübner, Jürgen Becker
2008	B	`conf`	A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. FPL Christopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hübner, Jürgen Becker
2008	A	`conf`	A self adaptive interfacing concept for consumer device integration into automotive entities. IPDPS Benjamin Glas, Alexander Klimm, Oliver Sander, Klaus D. Müller-Glaser, Jürgen Becker
2008	—	`conf`	Adaptive Reliable Chips - Reconfigurable Computing in the Nano Era. ISVLSI Jürgen Becker
2008	J	`jnl`	An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC. IEEE Des. Test Comput. Matthias Kühnle, Michael Hübner, Jürgen Becker, Antonio Deledda, Claudio Mucci, Florian Ries, Marcello Coppola, Lorenzo Pieralisi, Riccardo Locatelli, Giuseppe Maruccia, Tommaso DeMarco, Fabio Campi
2008	A	`conf`	An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores. IPDPS Alexander Klimm, Lars Braun, Jürgen Becker
2008	B	`conf`	Coarse-grained reconfiguration. FPL Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2008	Misc	`conf`	Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures. FCCM Carlos Morra, João Bispo, João M. P. Cardoso, Jürgen Becker
2008	A	`conf`	Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs. DATE Katarina Paulsson, Michael Hübner, Jürgen Becker
2008	J	`jnl`	Current Trends on Reconfigurable Computing. Int. J. Reconfigurable Comput. Jürgen Becker, Michael Hübner, Roger F. Woods, Philip Heng Wai Leong, Robert Esser, Lionel Torres
2008	B	`conf`	Data path driven waveform-like reconfiguration. FPL Lars Braun, Katarina Paulsson, Herrmann Krömer, Michael Hübner, Jürgen Becker
2008	—	`conf`	Data reallocation by exploiting FPGA configuration mechanisms. ARC Oliver Sander, Lars Braun, Michael Hübner, Jürgen Becker
2008	A	`conf`	Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems. DATE Jürgen Becker, Michael Hübner, Robert Esser, Andreas Herkersdorf, Walter Stechele, Vera Lauer
2008	A	`conf`	Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor. DATE Antonio Deledda, Claudio Mucci, Arseni Vitkovski, Philippe Bonnot, Arnaud Grasset, Philippe Millet, Matthias Kühnle, Florian Ries, Michael Hübner, Jürgen Becker, Massimo Coppola, Lorenzo Pieralisi, Riccardo Locatelli, Giuseppe Maruccia, Fabio Campi, Tommaso DeMarco
2008	B	`conf`	Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization. FPL Katarina Paulsson, Michael Hübner, Jürgen Becker
2008	—	`conf`	Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs. ISVLSI Katarina Paulsson, Ulrich Viereck, Michael Hübner, Jürgen Becker
2008	B	`conf`	Fine grain reconfigurable architectures. FPL Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker
2008	B	`conf`	New dimensions for multiprocessor architectures: Ondemand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach. FPL Diana Göhringer, Michael Hübner, Thomas Perschke, Jürgen Becker
2008	—	`conf`	Reducing latency times by accelerated routing mechanisms for an FPGA gateway in the automotive domain. FPT Oliver Sander, Michael Hübner, Jürgen Becker, Matthias Traub
2008	—	`conf`	Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures. SASP Carlos Morra, João M. P. Cardoso, João Bispo, Jürgen Becker
2008	A	`conf`	Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems. IPDPS Michael Hübner, Lars Braun, Diana Göhringer, Jürgen Becker
2008	A	`conf`	Runtime adaptive multi-processor system-on-chip: RAMPSoC. IPDPS Diana Göhringer, Michael Hübner, Volker Schatz, Jürgen Becker
2008	—	`conf`	Towards Novel Approaches in Design Automation for FPGA Power Optimization. PATMOS Juanjo Noguera, Robert Esser, Katarina Paulsson, Michael Hübner, Jürgen Becker
2007	A	`conf`	A General Purpose Partially Reconfigurable Processor Simulator (PReProS). IPDPS Alisson Vasconcelos de Brito, Matthias Kühnle, Elmar U. K. Melcher, Jürgen Becker
2007	B	`conf`	A Graphical Model-Level Debugger for Heterogenous Reconfigurable Architectures. FPL Philipp Graf, Michael Hübner, Klaus D. Müller-Glaser, Jürgen Becker
2007	B	`conf`	Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications. FPL Lars Braun, Michael Hübner, Jürgen Becker, Thomas Perschke, Volker Schatz, Stefan Bach
2007	A	`conf`	Communication Architectures for Dynamically Reconfigurable FPGA Designs. IPDPS Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle, Michael Hübner, Jürgen Becker
2007	J	`jnl`	Dynamic and Partial FPGA Exploitation. Proc. IEEE Jürgen Becker, Michael Hübner, Gerhard Hettich, Rainer Constapel, Joachim Eisenmann, Jürgen Luka
2007	—	`conf`	Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems. ReCoSoC Katarina Paulsson, Michael Hübner, Salih Bayar, Jürgen Becker
2007	B	`conf`	H.264 Decoder at HD Resolution on a Coarse Grain Dynamically Reconfigurable Architecture. FPL Mahendra Kumar Angamuthu Ganesan, Sundeep Singh, Frank May, Jürgen Becker
2007	J	`jnl`	Hardware Support for QoS-based Function Allocation in Reconfigurable Systems CoRR Michael Ullmann, Wansheng Jin, Jürgen Becker
2007	A	`conf`	High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs. IPDPS Maik Boden, Thomas Fiebig, Torsten Meibner, Steffen Rülke, Jürgen Becker
2007	B	`conf`	Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs. FPL Katarina Paulsson, Michael Hübner, Günther Auer, Michael Dreschmann, Jürgen Becker
2007	B	`conf`	MORPHEUS: Heterogeneous Reconfigurable Computing. FPL Florian Thoma, Matthias Kühnle, Philippe Bonnot, Elena Moscu Panainte, Koen Bertels, Sebastian Goller, Axel Schneider, Stéphane Guyetant, Eberhard Schüler, Klaus D. Müller-Glaser, Jürgen Becker
2007	—	`conf`	Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC. ISVLSI Alisson Vasconcelos de Brito, Matthias Kühnle, Michael Hübner, Jürgen Becker, Elmar U. K. Melcher
2007	J	`jnl`	New Adaptive Multi-grained Hardware Architecture for Processing of Dynamic Function Patterns (Neue adaptive multi-granulare Hardwarearchitektur). it Inf. Technol. Alexander Thomas, Jürgen Becker
2007	C	`conf`	New tool support and architectures in adaptive reconfigurable computing. VLSI-SoC Jürgen Becker, Adam Donlin, Michael Hübner
2007	B	`conf`	On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project. FPL Katarina Paulsson, Michael Hübner, Jürgen Becker, Jean-Marc Philippe, Christian Gamrat
2007	—	`conf`	Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. ISVLSI Michael Hübner, Lars Braun, Jürgen Becker, Christopher Claus, Walter Stechele
2007	A	`conf`	QUKU: A FPGA Based Flexible Coarse Grain Architecture Design Paradigm using Process Networks. IPDPS Sunil Shukla, Neil W. Bergmann, Jürgen Becker
2007	A	`conf`	Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements. IPDPS Carlos Morra, João M. P. Cardoso, Jürgen Becker
2007	B	`conf`	artNoC - A Novel Multi-Functional Router Architecture for Organic Computing. FPL Christian Schuck, Stefan Lamparth, Jürgen Becker
2006	—	`conf`	06141 Abstracts Collection -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas
2006	—	`conf`	06141 Executive Summary -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas
2006	A	`conf`	A high-level target-precise model for designing reconfigurable HW tasks. IPDPS Maik Boden, Steffen Rülke, Jürgen Becker
2006	—	`ed.`	ARCS 2006 - 19th International Conference on Architecture of Computing Systems, Workshops Proceedings, March 16, 2006, Frankfurt am Main, Germany ARCS Workshops Wolfgang Karl, Jürgen Becker, Karl-Erwin Großpietsch, Christian Hochberger, Erik Maehle
2006	A	`conf`	Communication concept for adaptive intelligent run-time systems supporting distributed reconfigurable embedded systems. IPDPS Michael Ullmann, Jürgen Becker
2006	—	`conf`	Digital On-Demand Computing Organism for Real-Time Systems. ARCS Workshops Jürgen Becker, Kurt Brändle, Uwe Brinkschulte, Jörg Henkel, Wolfgang Karl, Thorsten Köster, Michael Wenz, Heinz Wörn
2006	—	`conf`	Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager. ISVLSI Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon, Jürgen Becker
2006	—	`ed.`	Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006 Dynamically Reconfigurable Architectures Peter M. Athanas, Jürgen Becker, Gordon J. Brebner, Jürgen Teich
2006	A	`conf`	Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs. IPDPS Michael Hübner, Christian Schuck, Jürgen Becker
2006	—	`conf`	Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration. SBCCI Michael Hübner, Jürgen Becker
2006	B	`conf`	From Equation to VHDL: Using Rewriting Logic for Automated Function Generation. FPL Carlos Morra, M. Sackmann, Sunil Shukla, Jürgen Becker, Reiner W. Hartenstein
2006	—	`conf`	Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs. ISVLSI Katarina Paulsson, Michael Hübner, Markus Jung, Jürgen Becker
2006	—	`conf`	New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-time Adaptive Microelectronic Circuits. ISVLSI Michael Hübner, Christian Schuck, Matthias Kühnle, Jürgen Becker
2006	—	`conf`	On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives. SBCCI Katarina Paulsson, Michael Hübner, Jürgen Becker
2006	—	`conf`	Physical 2D Morphware and Power Reduction Methods for Everyone. Dynamically Reconfigurable Architectures Jürgen Becker, Michael Hübner, Katarina Paulsson
2006	—	`ed.`	Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006 SBCCI Claudionor José Nunes Coelho Jr., Ricardo P. Jacobi, Jürgen Becker
2006	—	`conf`	QUKU: A Coarse Grained Paradigm for FPGAs. Dynamically Reconfigurable Architectures Sunil Shukla, Neil W. Bergmann, Jürgen Becker
2006	—	`conf`	QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection. ARC Sunil Shukla, Neil W. Bergmann, Jürgen Becker
2006	—	`conf`	QUKU: A Two-Level Reconfigurable Architecture. ISVLSI Sunil Shukla, Neil W. Bergmann, Jürgen Becker
2006	—	`conf`	Run-time reconfigurabilility and other future trends. SBCCI Jürgen Becker, Michael Hübner
2006	—	`conf`	Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration. AHS Katarina Paulsson, Michael Hübner, Jürgen Becker
2006	—	`conf`	Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures. ReCoSoC Carlos Morra, M. Sackmann, Jürgen Becker, Reiner W. Hartenstein
2005	—	`ed.`	18th International Conference on Architecture of Computing Systems, Workshops, Innsbruck, Austria, March 2005 ARCS Workshops Uwe Brinkschulte, Jürgen Becker, Dietmar Fey, Christian Hochberger, Thomas Martinetz, Christian Müller-Schloer, Hartmut Schmeck, Theo Ungerer, Rolf P. Würtz
2005	—	`conf`	Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics. ReCoSoC Jürgen Becker, Michael Hübner, Katarina Paulsson, Alexander Thomas
2005	—	`conf`	Energy Model of Networks-on-Chip and a Bus. SoC Pascal T. Wolkotte, Gerard J. M. Smit, Nikolay Kavaldjiev, Jens E. Becker, Jürgen Becker
2005	B	`conf`	FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations. FPL Carlos Morra, Jürgen Becker, Mauricio Ayala-Rincón, Reiner W. Hartenstein
2005	A	`conf`	Hardware Enhanced Function Allocation Management in Reconfigurable Systems. IPDPS Michael Ullmann, Wansheng Jin, Jürgen Becker
2005	—	`conf`	Hardware/Software Co-Training Lab: From VHDL Bit-Level Coding up to CASE-Tool Based System Modeling. MSE Carsten Bieser, Klaus D. Müller-Glaser, Jürgen Becker
2005	—	`conf`	I Models and Tools for the Dynamic Reconfiguration of FPGAs. SoCC Adam Donlin, Jürgen Becker, Michael Hübner
2005	—	`conf`	Multi-Grained Reconfigurable Datapath Structures for Online-Adaptive Reconfigurable Hardware Architectures. ISVLSI Alexander Thomas, Jürgen Becker
2005	—	`conf`	Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures based on Xilinx Virtex-II FPGAs. ARCS Workshops Michael Hübner, Katarina Paulsson, Marcus Stitz, Jürgen Becker
2005	J	`jnl`	On-demand FPGA run-time system for flexible and dynamical reconfiguration. Int. J. Embed. Syst. Michael Ullmann, Michael Hübner, Jürgen Becker
2005	—	`conf`	Online-adaptive Reconfigurable Hardware Architecture and Runtime Environment. SoCC Alexander Thomas, Jürgen Becker
2005	—	`conf`	Overview of the 4S Project. SoC Gerard J. M. Smit, Eberhard Schüler, Jürgen Becker, Jérôme Quévremont, Werner Brugger
2005	A	`conf`	Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores. IPDPS Michael Hübner, Katarina Paulsson, Jürgen Becker
2005	A	`ed.`	Proceedings of The 2005 International Conference on Embedded Systems and Applications, ESA 2005, Las Vegas, Nevada, USA, June 27-30, 2005 ESA Laurence Tianruo Yang, Hamid R. Arabnia, Jürgen Becker, Masaharu Imai, Zoran A. Salcic
2005	J	`jnl`	Realtime configuration code decompression for dynamic FPGA self reconfiguration: evaluation and implementation. Int. J. Embed. Syst. Michael Hübner, Michael Ullmann, Jürgen Becker
2005	J	`jnl`	Rekonfigurierbare Hardware und intelligente Laufzeitsysteme für adaptives Rechnen. it Inf. Technol. Jürgen Becker, Kurt Brändle, Michael Ullmann
2005	B	`conf`	Run-Time Scheduling for Random Multi-Tasking in Reconfigurable Coprocessors. FPL Pascal Benoit, Jürgen Becker, Michel Robert, Lionel Torres, Gilles Sassatelli, Gaston Cambon
2005	J	`jnl`	Scalable Processor Instruction Set Extension. IEEE Des. Test Comput. Jürgen Becker, Alexander Thomas
2004	—	`ed.`	ARCS 2004 - Organic and Pervasive Computing, Workshops Proceedings, March 26, 2004, Augsburg, Germany ARCS Workshops Uwe Brinkschulte, Jürgen Becker, Dietmar Fey, Karl-Erwin Großpietsch, Christian Hochberger, Erik Maehle, Thomas A. Runkler
2004	—	`conf`	Adaptive DMA-based I/O interfaces for data stream handling in multi-grained reconfigurable hardware architectures. SBCCI Alexander Thomas, Thomas Zander, Jürgen Becker
2004	A	`conf`	An FPGA Run-Time System for Dynamical On-Demand Reconfiguration. IPDPS Michael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker
2004	—	`conf`	Aufbau- und Strukturkonzepte einer adaptive multigranularen rekonfigurierbaren Hardwarearchitektur. ARCS Workshops Alexander Thomas, Jürgen Becker
2004	A	`conf`	CARUSO - An Approach Towards a Network of Low Power Autonomic Systems on Chips for Embedded Real-time Application. IPDPS Uwe Brinkschulte, Jürgen Becker, Theo Ungerer
2004	—	`conf`	CARUSO - Project Goals and Principal Approach. GI Jahrestagung (2) Uwe Brinkschulte, Jürgen Becker, Klaus Dorfmüller-Ulhaas, Ralf König, Sascha Uhrig, Theo Ungerer
2004	—	`conf`	Coarse-grain reconfigurable XPP devices for adaptive high-end mobile video-processing. SoCC Jürgen Becker, Martin Vorbach
2004	J	`jnl`	Dagstuhl-Seminar "Dynamically and Partially Reconfigurable Architectures". it Inf. Technol. Jürgen Becker
2004	B	`conf`	Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures. FPL Alexander Thomas, Jürgen Becker
2004	B	`ed.`	Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings FPL Jürgen Becker, Marco Platzner, Serge Vernalde
2004	—	`conf`	Formale Verifikation eines Sonet/SDH Framers. MBMV Alexander Thomas, Jürgen Becker, Ulrich Heinkel, Klaus Winkelmann, Jörg Bormann
2004	A	`conf`	Hardware Support for QoS-based Function Allocation in Reconfigurable Systems. DATE Michael Ullmann, Wansheng Jin, Jürgen Becker
2004	B	`conf`	On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities. FPL Michael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker
2004	—	`conf`	Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration. SBCCI Michael Hübner, Tobias Becker, Jürgen Becker
2004	B	`conf`	Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems. FPL Michael Hübner, Michael Ullmann, Lars Braun, A. Klausmann, Jürgen Becker
2003	A	`conf`	An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture Integration. DATE Jürgen Becker, Alexander Thomas, Martin Vorbach, Volker Baumgarten
2003	—	`conf`	Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC). ISVLSI Jürgen Becker, Martin Vorbach
2003	—	`conf`	Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath. VLSI-SoC (Selected Papers) Jürgen Becker, Alexander Thomas, Maik Scheer
2003	J	`jnl`	Configware and morphware going mainstream. J. Syst. Archit. Jürgen Becker, Reiner W. Hartenstein
2003	C	`conf`	Datapath and Compiler Integration of Coarse-grain Reconfigurable XPP-Arrays into Pipelined RISC Processors. VLSI-SOC Jürgen Becker, Alexander Thomas, Maik Scheer
2003	—	`conf`	Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration. SBCCI Jürgen Becker, Alexander Thomas, Maik Scheer
2003	—	`conf`	Hardware/Software Co-Training by FPGA/ASIC Synthesis and programming of a RISC Microprocessor-Core. MSE Jens E. Becker, Carsten Bieser, Alexander Thomas, Klaus D. Müller-Glaser, Jürgen Becker
2003	—	`conf`	PACT XPP Architecture in Adaptive System-on-Chip Integration. Engineering of Reconfigurable Systems and Algorithms Jürgen Becker, Martin Vorbach
2003	—	`conf`	Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations. SBCCI Jürgen Becker, Michael Hübner, Michael Ullmann
2003	C	`conf`	Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations. VLSI-SOC Jürgen Becker, Michael Hübner, Michael Ullmann
2003	A	`conf`	Reconfigurable Processor Architectures for Mobile Phones. IPDPS Martin Vorbach, Jürgen Becker
2003	—	`conf`	Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems. VLSI-SoC (Selected Papers) Jürgen Becker, Michael Hübner, Michael Ullmann
2002	—	`conf`	Configurable Systems-on-Chip (CSoC). SBCCI Jürgen Becker
2002	—	`conf`	Configurable systems-on-chip: commercial and academic approaches. ICECS Jürgen Becker
2002	C	`conf`	Rapid Prototyping of FPGA Based Floating Point DSP Systems. IEEE International Workshop on Rapid System Prototyping Chun Hok Ho, Monk-Ping Leong, Philip Heng Wai Leong, Jürgen Becker, Manfred Glesner
2001	J	`jnl`	A Parallel Dynamically Reconfigurable Architecture Designed for Flexible Application-Tailored Hardware/Software Systems in Future Mobile Communication. J. Supercomput. Jürgen Becker, Manfred Glesner
2001	—	`conf`	Adaptive Systems-on-Chip: Architectures, Technologies and Applications. SBCCI Jürgen Becker, Thilo Pionteck, Manfred Glesner
2001	—	`conf`	Concept of a Joint University/Industry Course for Mixed-Signal System-On-Chip Design. MSE Jochen Mades, Thomas Schneider, André Windisch, Thomas Hollstein, Jürgen Becker, Manfred Glesner
2001	C	`conf`	Distributed Collaborative Design over Cave2 Framework. VLSI-SOC Leandro Soares Indrusiak, Jürgen Becker, Manfred Glesner, Ricardo Augusto da Luz Reis
2001	B	`conf`	Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures. FPL Jürgen Becker, Nicolas Liebau, Thilo Pionteck, Manfred Glesner
2001	—	`conf`	On the numerical accuracy of CORDIC-based frequency offset compensation in burst oriented OFDM systems. ICECS Lukusa D. Kabulepa, Tideya Kella, Thilo Pionteck, Ralf Ludewig, Jürgen Becker, J. Plechinger, Manfred Glesner
2001	C	`conf`	Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems. IEEE International Workshop on Rapid System Prototyping Amar Mukherjee, Nitin Motgi, Jürgen Becker, A. Friebe, C. Habermann, Manfred Glesner
2000	—	`conf`	A dynamically reconfigurable system-on-a-chip architecture for future mobile digital signal processing. EUSIPCO Ahmad Alsolaim, Jürgen Becker, Manfred Glesner, Janusz A. Starzyk
2000	—	`conf`	An Application-Tailored Dynamically Reconfigurable Hardware Architecture for Digital Baseband Processing. SBCCI Jürgen Becker, Thilo Pionteck, Manfred Glesner
2000	Misc	`conf`	Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems. FCCM Ahmad Alsolaim, Janusz A. Starzyk, Jürgen Becker, Manfred Glesner
2000	C	`conf`	Automated Communication Synthesis for Architecture-Precise Rapid Prototyping of Real-Time Embedded Systems. IEEE International Workshop on Rapid System Prototyping Frank-Michael Renner, Jürgen Becker, Manfred Glesner
2000	—	`conf`	Communication Performance Estimation and Communication Synthesis for Architecture-precise Prototyping of Real-time Embedded Systems. MBMV Frank-Michael Renner, Jürgen Becker, Manfred Glesner
2000	J	`jnl`	Communication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems. Des. Autom. Embed. Syst. Frank-Michael Renner, Jürgen Becker, Manfred Glesner
2000	B	`conf`	DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications. FPL Jürgen Becker, Thilo Pionteck, Manfred Glesner
2000	Misc	`conf`	Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures. PDPTA Jürgen Becker, Manfred Glesner, Ahmad Alsolaim, Janusz A. Starzyk
2000	B	`conf`	Field Programmable Communication Emulation and Optimization for Embedded System Design. FPL Frank-Michael Renner, Jürgen Becker, Manfred Glesner
2000	Misc	`conf`	IP-based Application Mapping Techniques for Dynamically Reconfigurable Hardware Architectures. PDPTA Jürgen Becker, Manfred Glesner
2000	C	`conf`	Simulation and Rapid Prototyping of Flexible Systems-on-a-Chip for Future Mobile Communication Applications. IEEE International Workshop on Rapid System Prototyping Jürgen Becker, Lukusa D. Kabulepa, Frank-Michael Renner, Manfred Glesner
2000	J	`jnl`	Synthese von Kommunikationsstrukturen und architekturgenaues Rapid-Prototyping eingebetteter Echtzeitsysteme (Communication Synthesis and Architecture-Precise Rapid Prototyping of Embedded systems with Hard Real-Time Constraints). Informationstechnik Tech. Inform. Frank-Michael Renner, Jürgen Becker, Andreas Kirschbaum, Manfred Glesner
1999	C	`conf`	Communication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems. IEEE International Workshop on Rapid System Prototyping Frank-Michael Renner, Jürgen Becker, Manfred Glesner
1999	B	`conf`	Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching. FPL Tri Caohuu, Thuy Trong Le, Manfred Glesner, Jürgen Becker
1999	—	`conf`	ILP-Based Board-Level Routing of Multi-Terminal Nets for Prototyping Reconfigurable Interconnect. VLSI Andreas Kirschbaum, Jürgen Becker, Manfred Glesner
1999	—	`conf`	Object-oriented Specification Approach for Synthesis of Hardware-/Software Systems. MBMV Matthias Meixner, Jürgen Becker, Thomas Hollstein, Manfred Glesner
1999	—	`conf`	Parallel Hardware Compilation in Complex Hardware/Software Systems based on High-Level Code Transformations. ARCS Marc Theisen, Jürgen Becker, Manfred Glesner, Tri Caohuu
1998	—	`conf`	A Reconfigurable Hardware-Monitor for Communication Analysis in Distributed Real-Time Systems. IPPS/SPDP Workshops Andreas Kirschbaum, Jürgen Becker, Manfred Glesner
1998	B	`conf`	An FPFA Implementation of a Magnetic Bearing Controller for Mechatronic Applications. FPL Frank-Michael Renner, Jürgen Becker, Manfred Glesner
1998	—	`conf`	Automatic Parallelism Exploitation for FPL-Based Accelerators. HICSS (7) Jürgen Becker, Karin Schmidt
1998	—	`conf`	HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems. CODES Thomas Hollstein, Jürgen Becker, Andreas Kirschbaum, Manfred Glesner
1998	—	`conf`	Internet-based Training of Reconfigurable Technologies. SBCCI Jürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner
1998	—	`conf`	Parallelization in Co-Compilation for Configurable Accelerators. ASP-DAC Jürgen Becker, Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger
1998	B	`conf`	Perspectives of Reconfigurable Computing in Research, Industry and Education. FPL Jürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner
1998	C	`conf`	Real-Time Prototyping in Microprocessor/Accelerator Symbiosis. International Workshop on Rapid System Prototyping Jürgen Becker, Reiner W. Hartenstein
1998	C	`conf`	Run-Time Monitoring of Communication Activities in a Rapid Prototyping Environment. International Workshop on Rapid System Prototyping Andreas Kirschbaum, Jürgen Becker, Manfred Glesner
1997	—	`conf`	A Novel Sequencer Hardware for Application Specific Computing. ASAP Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
1997	—	`conf`	A Novel Universal Sequencer Hardware. ARCS Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
1997	—	`conf`	A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators. HICSS (5) Reiner W. Hartenstein, Jürgen Becker
1997	—	`—`	A partitioning compiler for computers with Xputer-based accelerators. Jürgen Becker
1997	B	`conf`	Data scheduling to increase performance of parallel accelerators. FPL Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger
1997	Misc	`conf`	Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators. VLSI Design Reiner W. Hartenstein, Jürgen Becker
1997	—	`conf`	Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators. CODES Reiner W. Hartenstein, Jürgen Becker
1996	—	`conf`	A Partitioning Programming Environment for a Novel Parallel Architecture. IPPS Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger
1996	—	`conf`	A Synthesis System For Bus-Based Wavefront Array Architectures. ASAP Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger
1996	—	`conf`	An Embedded Accelerator for Real-Time Image Processing. RTS Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
1996	Misc	`conf`	CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. VLSI Design Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig
1996	B	`conf`	Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view. FPL Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
1996	J	`jnl`	High-performance computing using a reconfigurable accelerator. Concurr. Pract. Exp. Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig
1996	—	`conf`	Two-Level Hardware/Software Partitioning Using CoDe-X. ECBS Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
1996	—	`conf`	Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine. CODES Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
1995	—	`conf`	A Parallelizing Compilation Method for the Map-oriented Machine. ASAP Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt
1994	B	`conf`	Data-Procedural Languages for FPL-based Machines. FPL Andreas Ast, Jürgen Becker, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt