Jörg Schreiter

16 papers A* 1B 1C 1Journal 3Unranked 10

Year	Rank	Type	Title / Venue / Authors
2020	—	`conf`	A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM. COOL CHIPS Dennis Walter, André Scharfe, Alexander Oefelein, Florian Schraut, Heiner Bauer, Farkas Csaszar, Robert Niebsch, Jörg Schreiter, Holger Eisenreich, Sebastian Höppner
2020	J	`jnl`	Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology. IEEE Trans. Circuits Syst. II Express Briefs Sebastian Höppner, Holger Eisenreich, Dennis Walter, André Scharfe, Alexander Oefelein, Florian Schraut, Jörg Schreiter, Thorsten Riedel, Heiner Bauer, Robert Niebsch, Stephan Scherzer, Thomas Hocker, Stefan Scholze, Stephan Henker, Matthias Nossmann, Ulrich Hensel, Helmut Prengel
2020	J	`jnl`	Method for the Computer-Aided Schematic Design and Simulation of Hydrogel-Based Microfluidic Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andreas Voigt, Jörg Schreiter, Philipp Frank, Cesare Pini, Christian Mayr, Andreas Richter
2019	—	`conf`	How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC. ESSDERC Sebastian Höppner, Jörg Schreiter, Robert Niebsch, Stephan Scherzer, Ulrich Hensel, Jörg Winkler, Mario Orgis, Holger Eisenreich, Dennis Walter, Uwe Steeb, André Scharfe, Clifford Dmello, Robert Sinkwitz, Heiner Bauer, Alexander Oefelein, Florian Schraut
2016	A*	`conf`	An MPSoC for energy-efficient database query processing. DAC Sebastian Haas, Oliver Arnold, Benedikt Nöthen, Stefan Scholze, Georg Ellguth, Andreas Dixius, Sebastian Höppner, Stefan Schiefer, Stephan Hartmann, Stephan Henker, Thomas Hocker, Jörg Schreiter, Holger Eisenreich, Jens-Uwe Schlüßler, Dennis Walter, Tobias Seifert, Friedrich Pauls, Mattis Hasler, Yong Chen, Hermann Hensel, Sadia Moriam, Emil Matús, Christian Mayr, René Schüffny, Gerhard P. Fettweis
2004	—	`conf`	An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation. PARELEC Daniel Matolin, Jörg Schreiter, Stefan Getzlaff, René Schüffny
2004	—	`conf`	Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation. Image Processing: Algorithms and Systems Jörg Schreiter, Ulrich Ramacher, Arne Heittmann, Daniel Matolin, René Schüffny
2004	—	`conf`	Pulse coupled neural networks with adaptive synapses for image segmentation. ARCS Workshops Jörg Schreiter, Ulrich Ramacher, Arne Heittmann, Daniel Matolin, René Schüffny
2003	J	`jnl`	CMOS image sensor with mixed-signal processor array. IEEE J. Solid State Circuits Achim Graupner, Jörg Schreiter, Stefan Getzlaff, René Schüffny
2003	—	`conf`	High resolution ADPLL frequency synthesizer for FPGA-and ASIC-based applications. FPT Riad Stefo, Jörg Schreiter, Jens-Uwe Schluessler, René Schüffny
2002	C	`conf`	An Analog VLSI Pulsed Neural Network for Image Segmentation Using Adaptive Connection Weights. ICANN Arne Heittmann, Ulrich Ramacher, Daniel Matolin, Jörg Schreiter, René Schüffny
2002	—	`conf`	Analog implementation for networks of integrate-and-fire neurons with adaptive local connectivity. NNSP Jörg Schreiter, Ulrich Ramacher, Arne Heittmann, D. Matolini, René Schüffny
2001	—	`conf`	A system-on-chip realization of a CMOS image sensor with programmable analog image preprocessing. ISCAS (4) Stefan Getzlaff, Jörg Schreiter, Achim Graupner, René Schüffny
2001	—	`conf`	A vision device for image processing. SIP Achim Graupner, Stefan Getzlaff, Jörg Schreiter, René Schüffny
2001	—	`conf`	Minimizing charge injection errors in high-precision, high-speed SC-circuits. ISCAS (1) Jörg Krupar, Rico Srowik, Jörg Schreiter, Achim Graupner, René Schüffny, Udo Jörges
1999	B	`conf`	Design of parallel preprocessing image sensors. KES Jörg Schreiter, Rico Srowik, Achim Graupner, Stefan Getzlaff, René Schüffny