Jörg E. Vollrath

17 papers A 3C 3Journal 2Unranked 9
YearRankTypeTitle / Venue / Authors
2018 — conf
Open Access Microelectronics Course.
EWME
Jörg E. Vollrath
2015 C conf
An open access minimum automatic task generation live feedback system for electrical engineering.
EDUCON
Jörg E. Vollrath
2014 C conf
Interactive tools for teaching electrical engineering.
EDUCON
Jörg E. Vollrath
2013 C conf
Using models, simulation and measurements for teaching circuit design.
EDUCON
Jörg E. Vollrath
2006 — conf
DDR2 DRAM Output Timing Optimization.
MTDT
Jörg E. Vollrath, Jürg Schwizer, Marcin Gnat, Ralf Schneider, Bret Johnson
2006 A conf
DRAM-Specific Space of Memory Tests.
ITC
Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Georgi Gaydadjiev, Jörg E. Vollrath
2005 — conf
Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach.
Asian Test Symposium
Zaid Al-Ars, Said Hamdioui, Jörg E. Vollrath
2003 — conf
Output Timing Measurement Using an Idd Method.
MTDT
Jörg E. Vollrath
2003 J jnl
Testing and Characterization of SDRAMs.
IEEE Des. Test Comput.
Jörg E. Vollrath
2002 — conf
Signal Margin Analysis for Memory Sense Amplifiers .
DELTA
Jörg E. Vollrath
2001 J jnl
Compressed Bit Fail Maps for Memory Fail Pattern Classification.
J. Electron. Test.
Jörg E. Vollrath, Ulf Lederer, Thomas Hladschik
2001 A conf
Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment.
ITC
Jörg E. Vollrath, Randall Rooney
2000 — conf
Compressed bit fail maps for memory fail pattern classification.
ETW
Jörg E. Vollrath, Ulf Lederer, Thomas Hladschik
2000 — conf
Synchronous Dynamic Memory Test Construction: A Field Approach.
MTDT
Jörg E. Vollrath
1999 — conf
Tutorial: Characterizing SDRAMS.
MTDT
Jörg E. Vollrath
1998 — conf
Power Analysis of DRAMs.
Asian Test Symposium
Jörg E. Vollrath, Markus Huebl, Ernst Stahl
1997 A conf
Cell Signal Measurement for High-Density DRAMs.
ITC
Jörg E. Vollrath