Jörg Berthold

21 papers A 2C 2Journal 6Unranked 11
YearRankTypeTitle / Venue / Authors
2016 J jnl
Degradation and recovery of variability due to BTI.
Microelectron. Reliab.
Christian Schlünder, Jörg Berthold, Fabian Proebster, Andreas Martin, Wolfgang Gustin, Hans Reisinger
2011 C conf
Architecture and implementation of a Software-Defined Radio baseband processor.
ISCAS
Ulrich Ramacher, Wolfgang Raab, J. A. Ulrich Hachmann, Dominik Langen, Jörg Berthold, R. Kramer, A. Schackow, Cyprian Grassmann, Mirko Sauermann, P. Szreder, F. Capar, G. Obradovic, W. Xu, Nico Brüls, Kang Lee, Eugene Weber, Ray Kuhn, John Harrington
2010 A conf
Low power design of the X-GOLD
DATE
Wolfgang Raab, Jörg Berthold, J. A. Ulrich Hachmann, Dominik Langen, Michael Schreiner, Holger Eisenreich, Jens-Uwe Schluessler, Georg Ellguth
2007 J jnl
A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions.
IEEE J. Solid State Circuits
Thomas Lüftner, Jörg Berthold, Christian Pacha, Georg Georgakos, Guillaume Sauzon, Olaf Hömke, Jurij Beshenar, Peter Mahrla, Knut M. Just, Peter Hober, Stephan Henzler, Doris Schmitt-Landsiedel, Andre Yakovleff, Axel Klein, Richard J. Knight, Pramod Acharya, Andre Bonnardot, Steffen Buch, Matthias Sauer
2007 — conf
Efficiency of low-power design techniques in Multi-Gate FET CMOS Circuits.
ESSCIRC
Christian Pacha, Klaus von Arnim, Florian Bauer, Thomas Schulz, Wade Xiong, K. T. San, Andrew Marshall, Thomas Baumann, C. Rinn Cleavelin, Klaus Schruefer, Jörg Berthold
2007 J jnl
In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations.
IEEE J. Solid State Circuits
Matthias Eireiner, Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel
2007 — conf
Performance improvement of embedded low-power microprocessor cores by selective flip flop replacement.
ESSCIRC
Thomas Baumann, Jörg Berthold, T. Niedermeier, Tim Schoenauer, J. Dienstuhl, Doris Schmitt-Landsiedel, Christian Pacha
2006 — conf
A 90nm CMOS low-power GSM/EDGE multimedia-enhanced baseband processor with 380MHz ARM9 and mixed-signal extensions.
ISSCC
Thomas Lüftner, Jörg Berthold, Christian Pacha, Georg Georgakos, Guillaume Sauzon, Olaf Hömke, Jurij Beshenar, Peter Mahrla, Knut M. Just, Peter Hober, Stephan Henzler, Doris Schmitt-Landsiedel, Andre Yakovleff, Axel Klein, Richard J. Knight, Pramod Acharya, Hamid Mabrouki, Goulhamid Juhoor, Matthias Sauer
2006 — conf
Circuit design issues in multi-gate FET CMOS technologies.
ISSCC
Christian Pacha, Klaus von Arnim, Thomas Schulz, Weize Xiong, Michael Gostkowski, Gerhard Knoblinger, Andrew Marshall, Thomas Nirschl, Jörg Berthold, Christian Russ, Harald Gossner, Charvaka Duvvury, Paul Patruno, C. Rinn Cleavelin, Klaus Schruefer
2006 J jnl
Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead.
IEEE J. Solid State Circuits
Stephan Henzler, Georg Georgakos, Matthias Eireiner, Thomas Nirschl, Christian Pacha, Jörg Berthold, Doris Schmitt-Landsiedel
2005 — conf
Dynamic state-retention flip flop for fine-grained sleep-transistor scheme.
ESSCIRC
Stephan Henzler, Thomas Nirschi, Christian Pacha, Peter Spindler, Philip Teichmann, Michael Fulde, Jürgen Fischer, Matthias Eireiner, Thomas Fischer, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel
2005 J jnl
Efficiency of body biasing in 90-nm CMOS for low-power digital circuits.
IEEE J. Solid State Circuits
Klaus von Arnim, Eduardo Borinski, Peter Seegebrecht, Horst Fiedler, Ralf Brederlow, Roland Thewes, Jörg Berthold, Christian Pacha
2004 — conf
Efficiency of body biasing in 90 nm CMOS for low power digital circuits.
ESSCIRC
Klaus von Arnim, Eduardo Borinski, Peter Seegebrecht, Horst Fiedler, Ralf Brederlow, Roland Thewes, Jörg Berthold, Christian Pacha
2004 — conf
Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption.
PATMOS
Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel
2004 — conf
Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits.
PATMOS
Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel
2003 — conf
An ultra low-power adiabatic adder embedded in a standard 0.13μm CMOS environment.
ESSCIRC
Ettore Amirante, Jürgen Fischer, Markus Lang, Agnese Bargagli-Stoffi, Jörg Berthold, Christoph Heer, Doris Schmitt-Landsiedel
2003 C conf
Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off Schemes.
VLSI-SOC
Stephan Henzler, Markus Koban, Doris Schmitt-Landsiedel, Jörg Berthold, Georg Georgakos
2003 — conf
Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes.
VLSI-SoC (Selected Papers)
Stephan Henzler, Philip Teichmann, Markus Koban, Jörg Berthold, Georg Georgakos, Doris Schmitt-Landsiedel
2003 — conf
Reduced Leverage of Dual Supply voltages in Ultra Deep Submicron Technologies.
PATMOS
Tim Schoenauer, Jörg Berthold, Christoph Heer
1997 J jnl
The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits.
IEEE Trans. Very Large Scale Integr. Syst.
M. Eisele, Jörg Berthold, Doris Schmitt-Landsiedel, R. Mahnkopf
1996 A conf
The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits.
ISLPED
M. Eisele, Jörg Berthold, Doris Schmitt-Landsiedel, R. Mahnkopf