Jyotishman Saikia

11 papers A 2Misc 1Journal 4Unranked 4
YearRankTypeTitle / Venue / Authors
2024 J jnl
MACC-SRAM: A Multistep Accumulation Capacitor-Coupling In-Memory Computing SRAM Macro for Deep Convolutional Neural Networks.
IEEE J. Solid State Circuits
Bo Zhang, Jyotishman Saikia, Jian Meng, Dewei Wang, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-sun Seo, Mingoo Seok
2023 J jnl
A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity.
IEEE J. Solid State Circuits
Shreyas Kolala Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, Jae-sun Seo
2023 — conf
FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro.
ESSCIRC
Jyotishman Saikia, Amitesh Sridharan, Injune Yeo, Shreyas K. Venkataramanaiah, Deliang Fan, Jae-sun Seo
2023 J jnl
PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference.
IEEE J. Solid State Circuits
Bo Zhang, Shihui Yin, Minkyu Kim, Jyotishman Saikia, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-sun Seo, Mingoo Seok
2022 — conf
A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks.
CICC
Bo Zhang, Jyotishman Saikia, Jian Meng, Dewei Wang, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-sun Seo, Mingoo Seok
2022 — conf
A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification.
ESSCIRC
Shreyas Kolala Venkataramanaiah, Jian Meng, Han-Sok Suh, Injune Yeo, Jyotishman Saikia, Sai Kiran Cherupally, Yichi Zhang, Zhiru Zhang, Jae-sun Seo
2021 A conf
Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design.
DATE
Jyotishman Saikia, Shihui Yin, Sai Kiran Cherupally, Bo Zhang, Jian Meng, Mingoo Seok, Jae-sun Seo
2021 — conf
PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference.
VLSI Circuits
Shihui Yin, Bo Zhang, Minkyu Kim, Jyotishman Saikia, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Mingoo Seok, Jae-sun Seo
2019 A conf
K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM.
ISLPED
Jyotishman Saikia, Shihui Yin, Zhewei Jiang, Mingoo Seok, Jae-sun Seo
2018 J jnl
A Low-Overhead Dynamic TCAM With Pipelined Read-Restore Refresh Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sandeep Mishra, Telajala Venkata Mahendra, Jyotishman Saikia, Anup Dandapat
2017 Misc conf
A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access.
VLSID
Venkatesh Mani Tripathi, Sandeep Mishra, Jyotishman Saikia, Anup Dandapat