Jyi-Tsong Lin

11 papers Misc 2Journal 2Unranked 7
YearRankTypeTitle / Venue / Authors
2023 — conf
A Simple New Line-Tunneling iTFET with Overlapping Between Gate and Source Contact.
ASICON
Jyi-Tsong Lin, Kuan-Pin Lin
2023 — conf
An iTFET with Control Gate for Low Power Applications in RF and Digital Circuits.
ASICON
Ho-Hin Tse, Zheng-Hong Zhong, Jyi-Tsong Lin
2023 — conf
Steeper Subthreshold Swing Attained in Ge-Source Inductive Tunneling FET via Epitaxial Tunnel Layer for Suppressed Point Tunneling.
ASICON
Yen-Chen Chang, Wei-Heng Tai, Jyi-Tsong Lin
2020 — conf
Performances Improvement of Tunneling Field-Effect Transistors' with the Advanced Double-Gate PN Construction.
ICCE-TW
Yu-Jen Chen, Jyi-Tsong Lin
2018 Misc conf
Emerging FETs for Low Power and High Speed Embedded Dynamic Random Access Memory.
VLSID
Md. Hasan Raza Ansari, Nupur Navlakha, Jyi-Tsong Lin, Abhinav Kranti
2017 J jnl
Threshold-voltage variability analysis and modeling for junctionless double-gate transistors.
Microelectron. Reliab.
Chun-Yu Chen, Jyi-Tsong Lin, Meng-Hsueh Chiang
2015 — conf
Using GIDL mechanism for low-power consumption and data retention time improvement in a double-gate nanowire TFT 1T-DRAM with Fin-Gate and Pillar-Body structure.
ASICON
Wei-Han Lee, Jyi-Tsong Lin, Yu-Chun Wang, Po-Hsieh Lin, Chien-Chia Lai, Yong-Huang Lin, Tin-Chun Chang
2011 — conf
A unipolar-CMOS with recessed source/drain load.
ASICON
Jyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, Chih-Hung Sun, Tung-Yen Lai, Fu-Liang Yang
2008 J jnl
Analysis of Block Oxide Height Variations for a 40nm Gate Length bFDSOI-FET.
J. Comput.
Jyi-Tsong Lin, Yi-Chuen Eng
2007 Misc conf
Analysis of Si-body thickness variation for a new 40 nm gate length bFDSOI.
VLSI Design
Jyi-Tsong Lin, Yi-Chuen Eng, Tai-Yi Lee, Kao-Cheng Lin
2006 — conf
A New 1T DRAM Cell With Enhanced Floating Body Ef.
MTDT
Jyi-Tsong Lin, Mike Chang