Jwu E. Chen - RankMe

57 papers A 6B 1Misc 3Journal 20Unranked 27

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	Multiple Retest Systems for Screening High-Quality Chips. J. Electron. Test. Chung-Huang Yeh, Jwu E. Chen
2023	J	`jnl`	Prediction of the Test Yield of Future Integrated Circuits Through the Deductive Estimation Method. J. Circuits Syst. Comput. Chung-Huang Yeh, Jwu E. Chen
2023	J	`jnl`	Recycling Test Methods to Improve Test Capacity and Increase Chip Shipments. IEEE Des. Test Chung-Huang Yeh, Jwu E. Chen
2022	J	`jnl`	Application of Three-Repetition Tests Scheme to Improve Integrated Circuits Test Quality to Near-Zero Defect. Sensors Chung-Huang Yeh, Jwu E. Chen
2021	B	`conf`	Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering. ETS Katherine Shu-Min Li, Leon Li-Yang Chen, Ken Chau-Cheung Cheng, Peter Yi-Yu Liao, Sying-Jyan Wang, Andrew Yi-Ann Huang, Nova Cheng-Yen Tsai, Leon Chou, Gus Chang-Hung Han, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu
2021	A	`conf`	Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling. ITC Leon Li-Yang Chen, Katherine Shu-Min Li, Xu-Hao Jiang, Sying-Jyan Wang, Andrew Yi-Ann Huang, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu
2020	Misc	`conf`	Innovative Practice on Wafer Test Innovations. VTS Dyi-Chung Hu, Hirohito Hashimoto, Li-Fong Tseng, Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Sying-Jyan Wang, Sean Y.-S. Chen, Jwu E. Chen, Clark Liu, Andrew Yi-Ann Huang
2020	—	`conf`	The Decision Mechanism Uses the Multiple-Tests Scheme to Improve Test Yield in IC Testing. ITC-Asia Chung-Huang Yeh, Jwu E. Chen
2020	A	`conf`	Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis. DATE Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Andrew Yi-Ann Huang, Ji-Wei Li, Leon Li-Yang Chen, Nova Cheng-Yen Tsai, Sying-Jyan Wang, Chen-Shiun Lee, Leon Chou, Peter Yi-Yu Liao, Hsing-Chung Liang, Jwu E. Chen
2019	J	`jnl`	Repeated Testing Applications for Improving the IC Test Quality to Achieve Zero Defect Product Requirements. J. Electron. Test. Chung-Huang Yeh, Jwu E. Chen
2009	J	`jnl`	A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus. IEEE Trans. Very Large Scale Integr. Syst. Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2007	J	`jnl`	IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. J. Electron. Test. Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2007	J	`jnl`	Multilevel Full-Chip Routing With Testability and Yield Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2006	A	`conf`	A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs. ITC Shih Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu
2006	J	`jnl`	IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen
2006	—	`conf`	IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. ASP-DAC Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen
2005	—	`conf`	A Scan Matrix Design for Low Power Scan-Based Test. Asian Test Symposium Shih Ping Lin, Chung-Len Lee, Jwu E. Chen
2005	—	`conf`	Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing. Asian Test Symposium Shih Ping Lin, Chung-Len Lee, Jwu E. Chen
2005	—	`conf`	Finite State Machine Synthesis for At-Speed Oscillation Testability. Asian Test Symposium Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen
2005	—	`conf`	Multilevel full-chip routing with testability and yield enhancement. SLIP Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen
2005	—	`conf`	Oscillation ring based interconnect test scheme for SOC. ASP-DAC Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2004	—	`conf`	A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC. Asian Test Symposium Guan-Xun Chen, Chung-Len Lee, Jwu E. Chen
2004	—	`conf`	A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. Asian Test Symposium Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2003	J	`jnl`	Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits. J. Inf. Sci. Eng. Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen
2002	—	`conf`	A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal. Asian Test Symposium Ming Shae Wu, Chung-Len Lee, Chi Peng Chang, Jwu E. Chen
2002	A	`conf`	An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits. DATE Jun-Weir Lin, Chung-Len Lee, Jwu E. Chen
2002	J	`jnl`	Structural Fault Based Specification Reduction for Testing Analog Circuits. J. Electron. Test. Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen
2001	J	`jnl`	Fault Diagnosis for Linear Analog Circuits. J. Electron. Test. Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2001	—	`conf`	Guardband Determination for the Detection of Off-State and Junction Leakages in DRAM Testing. Asian Test Symposium Mill-Jer Wang, R.-L. Jiang, J.-W. Hsia, Chih-Hu Wang, Jwu E. Chen
2000	J	`jnl`	A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier. J. Inf. Sci. Eng. Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su
2000	—	`conf`	A case study of failure analysis and guardband determination for a 64M-bit DRAM. Asian Test Symposium Chin-Te Kao, Sam Wu, Jwu E. Chen
2000	—	`conf`	A methodology for fault model development for hierarchical linear systems. Asian Test Symposium Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu E. Chen, Chauchin Su
2000	—	`conf`	Fault diagnosis for linear analog circuits. Asian Test Symposium Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen
2000	—	`conf`	Is IDDQ testing not applicable for deep submicron VLSI in year 2011? Asian Test Symposium Chih-Wen Lu, Chauchin Su, Chung-Len Lee, Jwu E. Chen
2000	J	`jnl`	Oscillation Ring Delay Test for High Performance Microprocessors. J. Electron. Test. Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir
1999	J	`jnl`	A Compiled-Code Parallel Pattern Logic Simulator With Inertial Delay Model. J. Inf. Sci. Eng. Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen
1999	—	`conf`	A DFT for semi-DC fault diagnosis for switched-capacitor circuits. ETW Sheng-Jer Kuo, Chung Len Lee, Soon-Jyh Chang, Jwu E. Chen
1998	J	`jnl`	A Two-Phase Fault Simulation Scheme for Sequential Circuits. J. Inf. Sci. Eng. Wen Ching Wu, Chung-Len Lee, Jwu E. Chen
1998	A	`conf`	Maximization of power dissipation under random excitation for burn-in testing. ITC Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen
1998	Misc	`conf`	Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation. VTS Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
1997	—	`conf`	Fault diagnosis of odd-even sorting networks. Asian Test Symposium Chih Wei Hu, Chung-Len Lee, Wen Ching Wu, Jwu E. Chen
1997	Misc	`conf`	Functional test pattern generation for CMOS operational amplifier. VTS Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen
1997	J	`jnl`	Identifying invalid states for sequential circuit test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
1996	—	`conf`	Invalid State Identification for Sequential Circuit Test Generation. Asian Test Symposium Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
1996	—	`conf`	Yield Improvement by Test Error Cancellation. Asian Test Symposium Jwu E. Chen
1995	—	`conf`	Factorization of Multi-Valued Logic Functions. ISMVL Hui Min Wang, Chung-Len Lee, Jwu E. Chen
1995	—	`conf`	Fanout fault analysis for digital logic circuits. Asian Test Symposium Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen
1995	—	`conf`	Identification of robust untestable path delay faults. Asian Test Symposium Wen Ching Wu, Chung-Len Lee, Jwu E. Chen
1995	J	`jnl`	Identifying Untestable Faults in Sequential Circuits. IEEE Des. Test Comput. Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
1994	—	`conf`	Algebraic Division for Multilevel Logic Synthesis of Multi-Valued Logic Circuits. ISMVL Hui Min Wang, Chung-Len Lee, Jwu E. Chen
1994	—	`conf`	Complete Test Set for Multiple-Valued Logic Networks. ISMVL Hui Min Wang, Chung-Len Lee, Jwu E. Chen
1994	—	`conf`	Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning. EDAC-ETC-EUROASIC Wen Ching Wu, Chung-Len Lee, Jwu E. Chen, Won Yih Lin
1994	—	`conf`	TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator. EDAC-ETC-EUROASIC Meng Chiy Lin, Jwu E. Chen, Chung-Len Lee
1992	—	`conf`	Fault Analysis on Two-Level (K+1)-Valued Logic Circuits. ISMVL Hui Min Wang, Chung-Len Lee, Jwu E. Chen
1991	J	`jnl`	Checkpoints in irredundant two-level combinational circuits. J. Electron. Test. Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen
1991	J	`jnl`	Single-fault fault-collapsing analysis in sequential logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen
1990	A	`conf`	Single-fault fault collapsing analysis in sequential logic circuits. ITC Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen