Justin S. J. Wong

22 papers A 3B 4Journal 8Unranked 7
YearRankTypeTitle / Venue / Authors
2022 J jnl
Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network.
IEEE Trans. Neural Networks Learn. Syst.
Maolin Wang, Kelvin C. M. Lee, Bob M. F. Chung, Sharatchandra Varma Bogaraju, Ho-Cheung Ng, Justin S. J. Wong, Ho Cheung Shum, Kevin K. Tsia, Hayden Kwok-Hay So
2019 J jnl
A Real-Time Coprime Line Scan Super-Resolution System for Ultra-Fast Microscopy.
IEEE Trans. Biomed. Circuits Syst.
Runbin Shi, Justin S. J. Wong, Edmund Y. Lam, Kevin K. Tsia, Hayden Kwok-Hay So
2019 J jnl
High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing.
J. Imaging
Runbin Shi, Justin S. J. Wong, Hayden Kwok-Hay So
2017 — conf
Ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memory.
FPT
Justin S. J. Wong, Runbin Shi, Maolin Wang, Hayden Kwok-Hay So
2014 J jnl
Classification on variation maps: a new placement strategy to alleviate process variation on FPGA.
IEICE Electron. Express
Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
2014 J jnl
Mitigation of process variation effect in FPGAs with partial rerouting method.
IEICE Electron. Express
Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
2013 B conf
A variation-adaptive retiming method exploiting reconfigurability.
FPL
Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
2013 — conf
Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting.
FPT
Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
2013 J jnl
Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability.
IEEE Trans. Very Large Scale Integr. Syst.
Justin S. J. Wong, Peter Y. K. Cheung
2013 J jnl
Variation and Reliability in FPGAs.
IEEE Des. Test
Edward A. Stott, Zhenyu Guan, Joshua M. Levine, Justin S. J. Wong, Peter Y. K. Cheung
2012 B conf
A two-stage variation-aware placement method for FPGAS exploiting variation maps classification.
FPL
Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung
2011 A conf
Improved delay measurement method in FPGA based on transition probability.
FPGA
Justin S. J. Wong, Peter Y. K. Cheung
2011 — conf
Timing speculation in FPGAs: Probabilistic inference of data dependent failure rates.
FPT
Sumanta Chaudhuri, Justin S. J. Wong, Peter Y. K. Cheung
2010 B conf
Degradation Analysis and Mitigation in FPGAs.
FPL
Edward A. Stott, Justin S. J. Wong, Peter Y. K. Cheung
2010 A conf
Degradation in FPGAs: measurement and modelling.
FPGA
Edward A. Stott, Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung
2009 J jnl
Self-Measurement of Combinatorial Circuit Delays in FPGAs.
ACM Trans. Reconfigurable Technol. Syst.
Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung
2008 — conf
A transition probability based delay measurement method for arbitrary circuits on FPGAs.
FPT
Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung
2008 — conf
Characterisation of FPGA Clock Variability.
ISVLSI
N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung
2008 B conf
Combating process variation on FPGAS with a precise at-speed delay measurement method.
FPL
Justin S. J. Wong, Peter Y. K. Cheung, N. Pete Sedcole
2008 A conf
Measuring and modeling FPGA clock variability.
FPGA
N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung
2008 — conf
Modelling and compensating for clock skew variability in FPGAs.
FPT
N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung
2007 — conf
Self-characterization of Combinatorial Circuit Delays in FPGAs.
FPT
Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung