Justin E. Harlow III

11 papers A* 1A 3B 1Journal 4Unranked 2
YearRankTypeTitle / Venue / Authors
2007 J jnl
Architectures for Silicon Nanoelectronics and Beyond.
Computer
R. Iris Bahar, Dan W. Hammerstrom, Justin E. Harlow III, William H. Joyner Jr., Clifford Lau, Diana Marculescu, Alex Orailoglu, Massoud Pedram
2006 A conf
A novel approach for variation aware power minimization during gate sizing.
ISLPED
Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III
2003 — conf
Toward Design Technology in 2020: Trends, Issues, and Challenges.
ISVLSI
Justin E. Harlow III
2001 J jnl
Design of experiments and evaluation of BDD ordering heuristics.
Int. J. Softw. Tools Technol. Transf.
Justin E. Harlow III, Franc Brglez
2000 J jnl
Guest Editors' Introduction: Benchmarking for Design and Test.
IEEE Des. Test Comput.
Scott Davidson, Justin E. Harlow III
2000 J jnl
Overview of Popular Benchmark Sets.
IEEE Des. Test Comput.
Justin E. Harlow III
1999 — conf
Mirror, mirror, on the wall...is the new release any different at all? [BDDs].
ISCAS (6)
Justin E. Harlow III, Franc Brglez
1998 B conf
Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations.
FMCAD
Justin E. Harlow III, Franc Brglez
1998 A conf
Design of experiments in BDD variable ordering: lessons learned.
ICCAD
Justin E. Harlow III, Franc Brglez
1998 A conf
Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking.
DATE
Debabrata Ghosh, Nevin Kapur, Franc Brglez, Justin E. Harlow III
1977 A* conf
The open shop interactive mask design operation at harris semiconductor.
DAC
Justin E. Harlow III