Junzhong Shen

44 papers A* 4A 6B 4C 7Journal 15Unranked 8
YearRankTypeTitle / Venue / Authors
2026 J jnl
C-CIM: A Multi-Mode Convolution-Capable SRAM-CIM.
ACM Trans. Design Autom. Electr. Syst.
Renyu Yang, Xin Ju, Mei Wen, Jinjin Deng, Yi Wen, Junzhong Shen, Bin Liang, Tianyu Wang, Zhaoyan Shen, Zili Shao
2026 A* conf
Uni-STC: Unified Sparse Tensor Core.
HPCA
Haocheng Lian, Qiyue Zhang, Xinran Zhao, Meichen Dong, Yijie Nie, Zhengyi Zhao, Junzhong Shen, Wei Guo, Chun Huang, Bingcai Sui, Weifeng Liu
2025 C conf
CAMO: A High-Performance CIM-based Lightweight CNN Accelerator for Mobile Devices.
ISCAS
Xin Ju, Renyu Yang, Mei Wen, Junzhong Shen, Tianyu Wang, Zhaoyan Shen, Zili Shao, Bin Liang
2025 J jnl
FAMS: A FrAmework of Memory-Centric Mapping for DNNs on Systolic Array Accelerators.
IEEE Trans. Very Large Scale Integr. Syst.
Hao Sun, Junzhong Shen, Tian Zhang, Zhongyi Tang, Changwu Zhang, Yuhang Li, Yang Shi, Hengzhu Liu
2025 J jnl
ISOAcc: In-situ Shift Operation-based Accelerator For Efficient in-SRAM Multiplication.
ACM Trans. Design Autom. Electr. Syst.
Gaoyang Zhao, Junzhong Shen, Rongzhen Lin, Hua Li, Yaohua Wang
2025 B conf
Initial-Key Cache: An Efficient KV Cache Strategy Focusing on Initial and Key Tokens for LLMs.
IJCNN
Zhongyi Tang, Zejiang He, Junzhong Shen, Yiyue Hu, Luchen Zhou, Yongzhang Nie, Yongwen Wang
2025 J jnl
MAP-SIM: A DNN-Specific Mapping Optimization Framework for Shared-Memory CPU-Systolic Array Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuhang Li, Mei Wen, Junzhong Shen, Zhaoyun Chen, Yang Shi, Tianyu Wang, Zili Shao
2025 J jnl
SPSA: Exploring Sparse-Packing Computation on Systolic Arrays From Scratch.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Minjin Tang, Mei Wen, Jianchao Yang, Zeyu Xue, Junzhong Shen
2025 J jnl
SSpMM: Efficiently Scalable SpMM Kernels Across Multiple Generations of Tensor Cores.
IEEE Trans. Parallel Distributed Syst.
Zeyu Xue, Mei Wen, Jianchao Yang, Minjin Tang, Zhongdi Luo, Jing Feng, Yang Shi, Zhaoyun Chen, Junzhong Shen, Johannes Langguth
2025 A conf
SparSynergy: Unlocking Flexible and Efficient DNN Acceleration Through Multi-Level Sparsity.
DATE
Jingkui Yang, Mei Wen, Junzhong Shen, Jianchao Yang, Yasong Cao, Jun He, Minjin Tang, Zhaoyun Chen, Yang Shi
2025 A conf
WinAcc: Window-based Acceleration of Neural Networks Using Block Floating Point.
DATE
Xin Ju, Jun He, Mei Wen, Jing Feng, Yasong Cao, Junzhong Shen, Zhaoyun Chen, Yang Shi
2024 J jnl
ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core.
IEEE Trans. Very Large Scale Integr. Syst.
Yasong Cao, Mei Wen, Zhongdi Luo, Xin Ju, Haolan Huang, Junzhong Shen, Haiyan Chen
2024 — conf
BitShare: An Efficient Precision-Scalable Accelerator with Combining-Like-Terms GEMM.
ASAP
Yasong Cao, Mei Wen, Junzhong Shen, Zhongxing Li
2024 C conf
Enhancing the PE Utilization for Multi-Precision Systolic Array via Optimizing Computation Latency.
ISCAS
Jing Feng, Mei Wen, Xin Ju, Junzhong Shen, Yang Guo
2024 A* conf
HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs.
MICRO
Jianchao Yang, Mei Wen, Dong Chen, Zhaoyun Chen, Zeyu Xue, Yuhang Li, Junzhong Shen, Yang Shi
2024 A conf
MACO: Exploring GEMM Acceleration on a Loosely-Coupled Multi-Core Processor.
DATE
Bingcai Sui, Junzhong Shen, Caixia Sun, Junhui Wang, Zhong Zheng, Wei Guo
2024 J jnl
MACO: Exploring GEMM Acceleration on a Loosely-Coupled Multi-core Processor.
CoRR
Bingcai Sui, Junzhong Shen, Caixia Sun, Junhui Wang, Zhong Zheng, Wei Guo
2024 — conf
MAP-SIM: A Performance Model for Shared-Memory Heterogeneous Systems with Mapping Awareness.
ICA3PP (1)
Yuhang Li, Mei Wen, Junzhong Shen, Zhaoyun Chen, Yang Shi
2024 — conf
MSA
ICA3PP (3)
Minjin Tang, Mei Wen, Junzhong Shen, Jingkui Yang, Zeyu Xue, Zili Shao
2022 C conf
BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays.
ICCD
Jianchao Yang, Mei Wen, Junzhong Shen, Yasong Cao, Minjin Tang, Renyu Yang, Jiawei Fei, Chunyuan Zhang
2022 J jnl
BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays.
CoRR
Jianchao Yang, Mei Wen, Junzhong Shen, Yasong Cao, Minjin Tang, Renyu Yang, Jiawei Fei, Chunyuan Zhang
2022 — conf
MZ Core: An Enhanced Matrix Acceleration Engine for HPC/ AI Applications.
HPCC/DSS/SmartCity/DependSys
Yasong Cao, Mei Wen, Junzhong Shen, Sheng Liu, Zhi Wang, Minjin Tang, Yahao Fang, Jianchao Yang, Renyu Yang, Yuhan Kang, Jiawei Fei
2022 B conf
Mentha: Enabling Sparse-Packing Computation on Systolic Arrays.
ICPP
Minjin Tang, Mei Wen, Yasong Cao, Junzhong Shen, Jianchao Yang, Jiawei Fei, Yang Guo, Sheng Liu
2022 C conf
S-SIM: A Simulator for Systolic Array-based DNN Accelerators with Tile Access Awareness.
ISCAS
Yuhang Li, Mei Wen, Renyu Yang, Junzhong Shen, Yasong Cao, Jianan Wang
2022 B conf
TILE-SIM: A Systematic Approach to Systolic Array-based Accelerator Evaluation.
ISPASS
Yuhang Li, Mei Wen, Jiawei Fei, Junzhong Shen, Yasong Cao
2021 — conf
Embrace the Conflicts: Exploring the Integration of Single Port Memory in Systolic Array-based Accelerators.
HPCC/DSS/SmartCity/DependSys
Renyu Yang, Junzhong Shen, Mei Wen, Yasong Cao, Yuhang Li
2021 — conf
SAI: Self-Adjusting Incremental Quantile Estimation for Sparse Training of Neural Networks on Hardware Accelerators.
HPCC/DSS/SmartCity/DependSys
Jianchao Yang, Mei Wen, Minjin Tang, Junzhong Shen, Chunyuan Zhang
2020 J jnl
P4 to FPGA-A Fast Approach for Generating Efficient Network Processors.
IEEE Access
Zhuang Cao, Huayou Su, Qianming Yang, Junzhong Shen, Mei Wen, Chunyuan Zhang
2020 A conf
Scalable FPGA-based Architecture for High-Performance Per-Flow Traffic Measurement.
FPGA
Junzhong Shen, Mei Wen, Minjin Tang, Xiaolei Zhao, Chunyuan Zhang
2020 J jnl
Toward an Efficient Deep Pipelined Template-Based Architecture for Accelerating the Entire 2-D and 3-D CNNs on FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Junzhong Shen, You Huang, Mei Wen, Chunyuan Zhang
2020 A* conf
Towards Memory-Efficient Streaming Processing with Counter-Cascading Sketching on FPGA.
DAC
Minjin Tang, Mei Wen, Junzhong Shen, Xiaolei Zhao, Chunyuan Zhang
2020 — conf
Towards a Deep-Pipelined Architecture for Accelerating Deep GCN on a Multi-FPGA Platform.
ICA3PP (1)
Qixuan Cheng, Mei Wen, Junzhong Shen, Deguang Wang, Chunyuan Zhang
2019 A conf
Accelerating 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System.
FPGA
Junzhong Shen, Deguang Wang, You Huang, Mei Wen, Chunyuan Zhang
2019 B conf
An Efficient Design Flow for Accelerating Complicated-connected CNNs on a Multi-FPGA Platform.
ICPP
Deguang Wang, Junzhong Shen, Mei Wen, Chunyuan Zhang
2019 A* conf
Scale-out Acceleration for 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA System.
DAC
Junzhong Shen, Deguang Wang, You Huang, Mei Wen, Chunyuan Zhang
2019 C conf
Towards a Uniform Architecture for the Efficient Implementation of 2D and 3D Deconvolutional Neural Networks on FPGAs.
ISCAS
Deguang Wang, Junzhong Shen, Mei Wen, Chunyuan Zhang
2019 J jnl
Towards a Uniform Architecture for the Efficient Implementation of 2D and 3D Deconvolutional Neural Networks on FPGAs.
CoRR
Deguang Wang, Junzhong Shen, Mei Wen, Chunyuan Zhang
2018 J jnl
MALMM: A multi-array architecture for large-scale matrix multiplication on FPGA.
IEICE Electron. Express
You Huang, Junzhong Shen, Yuran Qiao, Mei Wen, Chunyuan Zhang
2018 C conf
Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs.
ISCAS
Junzhong Shen, Yuran Qiao, You Huang, Mei Wen, Chunyuan Zhang
2018 J jnl
Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs.
CoRR
Junzhong Shen, Yuran Qiao, You Huang, Mei Wen, Chunyuan Zhang
2018 A conf
Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA.
FPGA
Junzhong Shen, You Huang, Zelong Wang, Yuran Qiao, Mei Wen, Chunyuan Zhang
2017 J jnl
FPGA-accelerated deep convolutional neural networks for high throughput and energy efficiency.
Concurr. Comput. Pract. Exp.
Yuran Qiao, Junzhong Shen, Tao Xiao, Qianming Yang, Mei Wen, Chunyuan Zhang
2017 C conf
Optimizing OpenCL Implementation of Deep Convolutional Neural Network on FPGA.
NPC
Yuran Qiao, Junzhong Shen, Dafei Huang, Qianming Yang, Mei Wen, Chunyuan Zhang
2015 — conf
Unified Virtual Memory Support for Deep CNN Accelerator on SoC FPGA.
ICA3PP (1)
Tao Xiao, Yuran Qiao, Junzhong Shen, Qianming Yang, Mei Wen