Junyoung Song

39 papers C 1Journal 22Unranked 15
YearRankTypeTitle / Venue / Authors
2025 J jnl
A 1.58 pJ/b 9 G bps Reference-Less Clock and Data Recovery Circuit With Sigma Range Detector.
IEEE Trans. Circuits Syst. II Express Briefs
Jongchan An, Seung-Myeong Yu, Gwangmyeong An, Songi Cheon, Hyunsu Jang, Junyoung Song
2024 J jnl
A 0.7-pJ/b 12.5-Gb/s Reference-Less Subsampling Clock and Data Recovery Circuit.
IEEE Trans. Very Large Scale Integr. Syst.
Jongchan An, Seung-Myeong Yu, Gwangmyeong An, Bongsu Kim, Hyunsu Jang, Sewook Hwang, Junyoung Song
2024 J jnl
An 11 Gb/s 0.376 pJ/Bit Capacitor-Less Dicode Transceiver With Pattern-Dependent Equalizations TIA Termination for Parallel DRAM Interfaces.
IEEE Access
Hyunsu Park, Seung-Myeong Yu, Junyoung Song
2023 — conf
A Digital LDO with Adaptive Loop Control and Reset-Voltage Optimization for Comparator.
ISOCC
Gwangmyeong An, Juneho Yoon, Taeho Kim, Hyunsu Jang, Myeongju Park, Bongsu Kim, Jongchan An, Junyoung Song
2022 — conf
A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces.
ISSCC
Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Junyoung Song, Chulwoo Kim
2022 J jnl
Segmented Match-Line and Charge-Sharing Based Low-Cost TCAM.
IEEE Trans. Circuits Syst. II Express Briefs
Minseob Shim, Junwon Jeong, Junyoung Song, Yongtae Kim, Woong Choi
2021 J jnl
30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links.
IEEE J. Solid State Circuits
Hyunsu Park, Junyoung Song, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Jeongsik Yoo, Chulwoo Kim
2021 J jnl
A 0.88-pJ/bit 28Gb/s quad-rate 1-FIR 2-IIR decision feedback equalizer with 21dB loss compensation in 65nm CMOS process.
IEICE Electron. Express
Yunha Kang, Junyoung Song
2021 — conf
A 20-Gb/s Digitally Adaptive Linear Equalizer with 25dB loss for Single-ended Interfaces in 65nm CMOS.
ISOCC
Yunha Kang, Junyoung Song
2021 — conf
A 20Gb/s/pin Single-ended Transmitter with FEXT Compensation Technique.
ICEIC
Seung-Myeong Yu, Yunha Kang, Wooyoung Choi, Jongchan An, Junyoung Song
2021 — conf
A 28Gb/s quad-rate 1-FIR 2-IIR DFE with 20dB Loss Compensation in 65nm CMOS Process.
ICEIC
Yunha Kang, Seung-Myeong Yu, Jongchan An, Wooyoung Choi, Junyoung Song
2021 J jnl
A 32-Gb/s Dual-Mode Transceiver With One-Tap FIR and Two-Tap IIR RX Only Equalization in 65-nm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst.
Junyoung Song, Sewook Hwang, Chulwoo Kim
2021 — conf
Digital LDO with reference-less adaptive CLK generation and bit-shifting Coarse-Fine-control.
ISOCC
Wooyoung Choi, Seung-Myeong Yu, Yunha Kang, Junyoung Song
2019 J jnl
12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces.
IEEE J. Solid State Circuits
Yeonho Lee, Yoonjae Choi, Junyoung Song, Sewook Hwang, Sang-Geun Bae, Jaehun Jun, Chulwoo Kim
2019 — conf
A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface.
ISSCC
Hyunsu Park, Junyoung Song, Yeonho Lee, Jincheol Sim, Jonghyuck Choi, Chulwoo Kim
2019 J jnl
A 9 Gb/s/ch Transceiver With Reference-Less Data-Embedded Pseudo-Differential Clock Signaling for Graphics Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs
Junyoung Song, Yongtae Kim, Chulwoo Kim
2019 J jnl
A ΔΣ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth.
IEEE Trans. Circuits Syst. II Express Briefs
Sang-Geun Bae, Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim
2018 J jnl
A 1-V 10-Gb/s/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap.
Junyoung Song, Sewook Hwang, Hyun-Woo Lee, Chulwoo Kim
2017 — conf
29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces.
ISSCC
Yeonho Lee, Yoonjae Choi, Sang-Geun Bae, Jaehun Jun, Junyoung Song, Sewook Hwang, Chulwoo Kim
2017 J jnl
A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim
2017 J jnl
A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique.
IEEE Trans. Very Large Scale Integr. Syst.
Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Chulwoo Kim
2017 J jnl
A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM.
IEEE Trans. Circuits Syst. II Express Briefs
Jungtaek You, Junyoung Song, Chulwoo Kim
2017 J jnl
A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs
Jayoung Kim, Junyoung Song, Jungtaek You, Sewook Hwang, Sang-Geun Bae, Chulwoo Kim
2016 — conf
A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE.
VLSI Circuits
Sewook Hwang, Sungjun Moon, Junyoung Song, Chulwoo Kim
2016 J jnl
A 4×5-Gb/s 1.12-µs Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels.
IEEE Trans. Very Large Scale Integr. Syst.
Junyoung Song, Sewook Hwang, Chulwoo Kim
2016 J jnl
An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers.
IEEE Trans. Very Large Scale Integr. Syst.
Sewook Hwang, Junyoung Song, Sang-Geun Bae, Yeonho Lee, Chulwoo Kim
2015 — conf
17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces.
ISSCC
Junyoung Song, Hyun-Woo Lee, Jayoung Kim, Sewook Hwang, Chulwoo Kim
2014 — conf
25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector.
ISSCC
Hyun-Woo Lee, Junyoung Song, Sangah Hyun, Seunggeun Baek, Yuri Lim, Jungwan Lee, Minsu Park, Haerang Choi, Changkyu Choi, Jin-Youp Cha, Jaeil Kim, Hoon Choi, Seung-Wook Kwack, Yonggu Kang, Jongsam Kim, Junghoon Park, Jonghwan Kim, Jin-Hee Cho, Chulwoo Kim, Yunsaing Kim, Jaejin Lee, Byong-Tae Chung, Sung-Joo Hong
2014 J jnl
A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- µm CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs
Junyoung Song, Sewook Hwang, Hyun-Woo Lee, Chulwoo Kim
2014 J jnl
An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator.
IEEE Trans. Very Large Scale Integr. Syst.
Kyeong-Min Kim, Sewook Hwang, Junyoung Song, Chulwoo Kim
2014 — book
High-Bandwidth Memory Interface
Chulwoo Kim, Hyun-Woo Lee, Junyoung Song
2013 J jnl
A 1.62 Gb/s-2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection.
IEEE Trans. Circuits Syst. I Regul. Pap.
Junyoung Song, Inhwa Jung, Minyoung Song, Young-Ho Kwak, Sewook Hwang, Chulwoo Kim
2013 J jnl
A 247 µW 800 Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon via (TSV) Interface.
IEEE J. Solid State Circuits
Soo-Bin Lim, Hyun-Woo Lee, Junyoung Song, Chulwoo Kim
2013 — conf
A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process.
ASP-DAC
Junyoung Song, Hyun-Woo Lee, Sewook Hwang, Inhwa Jung, Chulwoo Kim
2013 — conf
An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface.
ISSCC
Junyoung Song, Hyun-Woo Lee, Soo-Bin Lim, Sewook Hwang, Yunsaing Kim, Young-Jung Choi, Byong-Tae Chung, Chulwoo Kim
2013 J jnl
Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip.
IEEE Trans. Very Large Scale Integr. Syst.
Phi-Hung Pham, Junyoung Song, Jongsun Park, Chulwoo Kim
2012 — conf
A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface.
ISSCC
Hyun-Woo Lee, Soo-Bin Lim, Junyoung Song, Jabeom Koo, Dae-Han Kwon, Jong-Ho Kang, Yunsaing Kim, Young-Jung Choi, Kunwoo Park, Byong-Tae Chung, Chulwoo Kim
2012 C conf
A 5.4Gb/s adaptive equalizer with unit pulse charging technique in 0.13µm CMOS.
ISCAS
Sewook Hwang, Inhwa Jung, Junyoung Song, Chulwoo Kim
2009 — conf
Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application.
CICC
Jabeom Koo, Gil-Su Kim, Junyoung Song, Kwan-Weon Kim, Young-Jung Choi, Chulwoo Kim