Junyan Ren - RankMe

215 papers A* 1B 2C 36Journal 56Unranked 120

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A 24V-to-1V Triple Series-Capacitor Buck Converter With Low-Voltage Power Switches. IEEE Trans. Circuits Syst. II Express Briefs Weidong Xue, Xinwei Yu, Yisen Zhang, Junyan Ren
2025	C	`conf`	A 4.8dB NF, 3-to-119GHz Distributed LNA With Three-Turn Transformer and Multiple Magnetic Coupling Feedback Network in 28nm CMOS. ISCAS Yujia Wang, Jincheng Zhang, Shunli Ma, Junyan Ren
2025	J	`jnl`	A Comprehensive Digital Calibration for Pipelined ADCs Using Cascaded Nonlinearity Correction. IEEE Trans. Very Large Scale Integr. Syst. Yuguo Xiang, Dayan Zhou, Minjia Song, Danfeng Zhai, Jingchao Lan, Junyan Ren, Fan Ye
2025	J	`jnl`	A Harmonic-Suppressed GaN Power Amplifier Using Artificial Coupled Resonator. IEEE Trans. Very Large Scale Integr. Syst. Letian Guo, Jincheng Zhang, Lihe Nie, Jian Wang, Yong Chen, Junyan Ren, Shunli Ma
2025	J	`jnl`	A Low-Power and High-Efficiency Neural Network Based Scheme for Nonlinearity and Memory Effects in Single-Channel ADCs. IEEE Trans. Circuits Syst. II Express Briefs Yuguo Xiang, Danfeng Zhai, Junyan Ren, Fan Ye
2025	C	`conf`	An Effective Digital Calibration Method Based on Volterra Neural Network for Pipeline ADCs. ISCAS Yuguo Xiang, Danfeng Zhai, Junyan Ren, Fan Ye
2024	J	`jnl`	A 3.0-V 4.2-μA 2.23-ppm/°C BGR with cross-connected NPNs and base-current compensation. Microelectron. J. Weidong Xue, Xinwei Yu, Yisen Zhang, Xin Ming, Jian Fang, Junyan Ren
2024	C	`conf`	Hardware-Implemented Calibration Based on Sinusoidal Fitting for Hybrid Pipeline ADC. ISCAS Yuguo Xiang, Yutong Zhao, Dayan Zhou, Danfeng Zhai, Junyan Ren, Fan Ye
2023	J	`jnl`	28-nm CMOS Ultrasound AFE With Split Attenuation for Optimizing Gain-Range, Noise, and Area. IEEE Trans. Circuits Syst. I Regul. Pap. Xinwei Yu, Zhi Chen, Siqing Wu, Lulu Liu, Hao Chi, Fan Ye, Junyan Ren
2023	—	`conf`	A 15GHz Class-C VCO with Two-stage Buffer in 0.15-μm GaAs. ASICON Lei Wu, Junyan Ren, Tianxiang Wu, Shunli Ma
2023	—	`conf`	A 300MS/s 57.6dB SNDR Single-Channel SAR ADC with Accelerated SAR Logic. ASICON Muxi Zou, Shunli Ma, Xiaodi Feng, Junyan Ren, Tianxiang Wu
2023	J	`jnl`	A 4.5-W, 18.5-24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique. IEEE Trans. Very Large Scale Integr. Syst. Yujia Wang, Jincheng Zhang, Yong Chen, Junyan Ren, Shunli Ma
2023	C	`conf`	A 400-MS/s 12-bit Voltage-Time Hybrid ADC with a Ping-Pong SAR TDC for Speed Enhancement. ISCAS Yutong Zhao, Yuguo Xiang, Fan Ye, Junyan Ren
2023	—	`conf`	A 6-Gb/s Wireline Transmitter Design with 3-Tap FFE in 28nm CMOS Technology. ASICON Bingrong Lyu, Fan Ye, Junyan Ren
2023	J	`jnl`	A 90- to 115-GHz superheterodyne receiver front-end for W-band imaging system in 28-nm complementary metal-oxide-semiconductor. Int. J. Circuit Theory Appl. Xi Wang, Dong Wei, Zhiyang Zhang, Tianxiang Wu, Xu Chen, Yong Chen, Junyan Ren, Shunli Ma
2023	—	`conf`	A Multi-channel 12-bits 100MS/s SAR ADC in 65nm CMOS. ASICON Yigang Wei, Tianxiang Wu, Shunli Ma, Junyan Ren
2023	—	`conf`	A Three-stage Analog Low-Frequency Drift Calibration and DC Offset Correction Circuit for Ultrasonic AFE. ASICON Siqing Wu, Xinwei Yu, Xingtao Zhu, Fan Ye, Junyan Ren
2023	J	`jnl`	Low-Noise Low-Power Ultrasound AFE With Continuous TGC Built in Both TIA and Beamformer. IEEE Trans. Biomed. Circuits Syst. Xinwei Yu, Yan Wang, Fan Ye, Junyan Ren
2022	J	`jnl`	A 10-MHz to 50-GHz low-jitter multiphase clock generator for high-speed oscilloscope in 0.15-μm GaAs technology. Int. J. Circuit Theory Appl. Tianxiang Wu, Xi Wang, Yong Chen, Junyan Ren, Shunli Ma
2022	—	`conf`	A 134-154 GHz Low-Noise Amplifier Achieving 36.3-dB Maximum Gain with 3.8-dB Minimum Noise Figure for D-Band Imaging System. MWSCAS Xi Wang, Zhiyang Zhang, Junyan Ren, Shunli Ma
2022	C	`conf`	A 2.5-GS/s Time-Interleaved SAR-Assisted Ringamp-Based Pipelined ADC with Digital Background Calibration. ISCAS Jingchao Lan, Danfeng Zhai, Yongzhen Chen, Zhekan Ni, Xingchen Shen, Fan Ye, Junyan Ren
2022	J	`jnl`	A 23- to 28-GHz 5-bit switch-type phase shifter with 1-bit calibration based on optimized ABCD matrix design methods for 5G MIMO system in 0.15-μm GaAs. Int. J. Circuit Theory Appl. Zhiyang Zhang, Lihe Nie, Jincheng Zhang, Tianxiang Wu, Yong Chen, Junyan Ren, Shunli Ma
2022	—	`conf`	A 500-MS/s 9-Bit Time-Domain ADC Using a Nonbinary Successive Approximation TDC. APCCAS Yutong Zhao, Fan Ye, Junyan Ren
2022	J	`jnl`	A 6.5-mm IEEE Trans. Circuits Syst. II Express Briefs Jincheng Zhang, Lihe Nie, Yong Chen, Junyan Ren, Shunli Ma
2022	—	`conf`	A 60-GHz CMOS Balanced Power Amplifier with Miniaturized Quadrature Hybrids Achieving 19.0-dBm Output Power and 24.4% Peak PAE. APCCAS Zhiyang Zhang, Xi Wang, Yong Chen, Junyan Ren, Shunli Ma
2022	—	`conf`	A Branch-Gain-Balanced LNA Based on Voltage- Controlled Resistor Feedback and Shared CMFB Amplifier. MWSCAS Lulu Liu, Yimin Wu, Xinwei Yu, Fan Ye, Junyan Ren
2022	—	`conf`	A Broadband LMS-based Band-split Crosstalk Cancellation Method for Ultrasound Systems. MWSCAS Wenhan Lu, Yimin Wu, Fan Ye, Junyan Ren
2022	—	`conf`	A Low Noise TIA with Continuous Time-Gain Compensation for Ultrasound Transducers. APCCAS Xinwei Yu, Fan Ye, Junyan Ren
2022	—	`conf`	A Single-Channel 1.25-GS/s 11-bit Pipelined ADC with Robust Floating-Powered Ring Amplifier and First-Order Gain Error Calibration. MWSCAS Jingchao Lan, Yuxuan Zhang, Fan Ye, Junyan Ren
2022	C	`conf`	A Two-Way Current-Combining W-band Power Amplifier Achieving 17.4-dBm Output Power with 19.4% PAE in 65-nm Bulk CMOS. ISCAS Zhiyang Zhang, Xi Wang, Junyan Ren, Shunli Ma
2022	J	`jnl`	Effective Gain Analysis and Statistic Based Calibration for Ring Amplifier With Robustness to PVT Variation. IEEE Trans. Circuits Syst. II Express Briefs Jingchao Lan, Yongzhen Chen, Xingchen Shen, Zhekan Ni, Yimin Wu, Fan Ye, Junyan Ren
2022	J	`jnl`	High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion. IEEE Trans. Circuits Syst. I Regul. Pap. Danfeng Zhai, Wenning Jiang, Xinru Jia, Jingchao Lan, Mingqiang Guo, Sai-Weng Sin, Fan Ye, Qi Liu, Junyan Ren, Chixiao Chen
2022	J	`jnl`	Sensitivity - Bandwidth Optimization of PMUT with Acoustical Matching Using Finite Element Method. Sensors Leming He, Weijiang Xu, Yan Wang, Jia Zhou, Junyan Ren
2021	J	`jnl`	A 12-bit 100MS/s SAR ADC With Equivalent Split-Capacitor and LSB-Averaging in 14-nm CMOS FinFET. IEEE Access Yan Zheng, Jingchao Lan, Fan Ye, Junyan Ren
2021	J	`jnl`	A 120-150 GHz Power Amplifier in 28-nm CMOS Achieving 21.9-dB Gain and 11.8-dBm P IEEE Access Jincheng Zhang, Tianxiang Wu, Lihe Nie, Shunli Ma, Yong Chen, Junyan Ren
2021	—	`conf`	A 3-to-78GHz Differential Distributed Amplifier with Ultra- Balanced Active Balun and Gain Boosting Techniques in 65-nm CMOS Process. A-SSCC Jincheng Zhang, Tianxiang Wu, Yong Chen, Junyan Ren, Shunli Ma
2021	—	`conf`	A 35-to-50 GHz CMOS Low-Noise Amplifier with 22.2% -1-dB Fractional Bandwidth and 30.5-dB Maximum Gain for 5G New Radio. ESSCIRC Dong Wei, Tianxiang Wu, Shunli Ma, Yong Chen, Junyan Ren
2021	—	`conf`	A 5-bit High-Linearity, Binary-Recombination-Redundancy Sub-SAR ADC in 300MS/s, 14-bit Pipelined-SAR ADC. ASICON Guoyao Wu, Ziwei Li, Yutong Zhao, Fan Ye, Junyan Ren
2021	J	`jnl`	A 5G Wireless Event-Driven Sensor Chip for Online Power-Line Disturbances Detecting Network in 0.25 μm GaAs Process. IEEE Trans. Ind. Electron. Shunli Ma, Tianxiang Wu, Jincheng Zhang, Junyan Ren
2021	J	`jnl`	A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS. IEEE Access Manxin Li, Yuting Yao, Biao Hu, Jipeng Wei, Yong Chen, Shunli Ma, Fan Ye, Junyan Ren
2021	—	`conf`	A 68.36 dB 12 bit 100MS/s SAR ADC with a low-noise comparator in 14-nm CMOS FinFet. ASICON Yan Zheng, Jingchao Lan, Fan Ye, Junyan Ren
2021	—	`conf`	A 79GHz 5-bit Phase Shifter With π-Network in 28-nm CMOS. ASICON Xu Chen, Junyan Ren, Shunli Ma
2021	J	`jnl`	A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Yuefeng Cao, Shumin Zhang, Tianli Zhang, Yongzhen Chen, Yutong Zhao, Chixiao Chen, Fan Ye, Junyan Ren
2021	—	`conf`	A C-Band Power Amplifier with Over-Neutralization Technique and Coupled-Line MCR Matching Methods for 5G Communication in 0.25-μm GaAs. ASICON Zhiyang Zhang, Junyan Ren, Shunli Ma
2021	—	`conf`	A Hardware-Efficient Calibrator for SAR-Pipelined ADCs with a Layer-based Sharing Neural Network. MWSCAS Min Chen, Nuo Xu, Yutong Zhao, Fan Ye, Junyan Ren
2021	—	`conf`	A High Linearity Bootstrapped Switch with Leakage Current Suppressed for GS/s Sampling Rate ADC. ISOCC Jingchao Lan, Yan Zheng, Yimin Wu, Min Chen, Fan Ye, Junyan Ren
2021	—	`conf`	A High Linearity and Low Noise Anti-Aliasing Filter for ADCs. ASICON Hao Chi, Jun Xu, Fan Ye, Junyan Ren
2021	—	`conf`	A Novel Ring Amplifier with Low Common-Mode Voltage Variation and Noise Reduction Using Floating Power Technique. MWSCAS Jingchao Lan, Yan Zheng, Yimin Wu, Fan Ye, Junyan Ren
2021	C	`conf`	A Partially Binarized and Fixed Neural Network Based Calibrator for SAR-Pipelined ADCs Achieving 95.0-dB SFDR. ISCAS Min Chen, Yutong Zhao, Nuo Xu, Fan Ye, Junyan Ren
2021	—	`conf`	A Three-Stage Comparator with High Speed and Low Power. ASICON Jingqi Wang, Fan Ye, Junyan Ren
2021	—	`conf`	A Wide-Range 12b 150MS/s P-SAR ADC with Open-Loop Residue Amplifier for Ultrasound AFE. ASICON Ziwei Li, Yutong Zhao, Guoyao Wu, Fan Ye, Junyan Ren
2021	—	`conf`	Additive Neural Network Based Static and Dynamic Distortion Modeling for Prior-Knowledge-Free Nyquist ADC Characterization. MWSCAS Danfeng Zhai, Peizhe Li, Jiushan Zhang, Chixiao Chen, Fan Ye, Junyan Ren
2021	C	`conf`	An 11-Bit 500 MS/s Two-Step SAR ADC with Non-Attenuated Passive Residue Transfer. ISCAS Wenbin He, Fan Ye, Junyan Ren
2021	—	`conf`	An 4 ASICON Xi Wang, Junyan Ren, Shunli Ma
2021	J	`jnl`	Analysis and Design of a 35-GHz Hybrid π-Network High-Gain Phase Shifter With 360° Continuous Phase Shifting. IEEE Access Dong Wei, Xuan Ding, Hai Yu, Yen-Cheng Kuan, Qun Jane Gu, Zhiwei Xu, Shunli Ma, Junyan Ren
2021	J	`jnl`	Development of Broadband High-Frequency Piezoelectric Micromachined Ultrasonic Transducer Array. Sensors Xubo Wang, Leming He, You-Cao Ma, Wenjuan Liu, Weijiang Xu, Junyan Ren, Antoine Riaud, Jia Zhou
2021	—	`conf`	Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration. ISOCC Danfeng Zhai, Chixiao Chen, Liang Qi, Fan Ye, Junyan Ren
2021	—	`conf`	Resistive Degeneration Linearization Dynamic Residue Amplifiers for Pipelined ADCs. ISOCC Ziwei Li, Guoyao Wu, Yutong Zhao, Fan Ye, Junyan Ren
2020	—	`conf`	A 10-18 GHz GaN Power Amplifier Based on Asymmetric Magnetically Coupled Resonator. MWSCAS Jincheng Zhang, Lihe Nie, Shunli Ma, Junyan Ren
2020	—	`conf`	A 12-bit SAR ADC Using Pseudo-Dynamic Weighting C-DAC for Capacitor Error Calibration. MWSCAS Fan Ye, Junyan Ren
2020	C	`conf`	A 13 Bit 100 MS/s SAR ADC with 74.57 dB SNDR in 14-nm CMOS FinFET. ISCAS Yan Zheng, Fan Ye, Junyan Ren
2020	—	`conf`	A 16-channel 50MS/s 14bit Pipelined-SAR ADC for Integrated Ultrasound Imaging Systems. APCCAS Yimin Wu, Jingchao Lan, Min Chen, Fan Ye, Junyan Ren
2020	—	`conf`	A Calibration Scheme for Nonlinearity of the SAR-Pipelined ADCs Based on a Shared Neural Network. APCCAS Min Chen, Yimin Wu, Jingchao Lan, Fan Ye, Chixiao Chen, Junyan Ren
2020	—	`conf`	A Fast Response Reference Voltage Buffer for 12b 200MS/s SAR ADC. MWSCAS Wenbin He, Fan Ye, Junyan Ren
2020	—	`conf`	A Low Power Reference Voltage Buffer and High Density Unit capacitor in a 12b 200MS/s SAR ADC. APCCAS Wenbin He, Ziwei Li, Fan Ye, Junyan Ren
2020	—	`conf`	A Low-Power Low-Noise Dynamic Comparator With Latch-Embedding Floating Amplifier. APCCAS Ziwei Li, Wenbin He, Fan Ye, Junyan Ren
2020	J	`jnl`	A Quadrature PLL With Phase Mismatch Calibration for 32GS/s Time-Interleaved ADC. IEEE Access Shunli Ma, Tianxiang Wu, Junyan Ren
2020	—	`conf`	An Area-Power-Efficient AFE with NS-SAR ADC For High-Frequency Ultrasound Applications. APCCAS Yimin Wu, Shuai Li, Longheng Luo, Fan Ye, Junyan Ren
2020	J	`jnl`	Analog Integrated Circuits Based on Wafer-Level Two-Dimensional MoS IEEE Access Shunli Ma, Yan Wang, Xinyu Chen, Tianxiang Wu, Xi Wang, Hongwei Tang, Yuting Yao, Hao Yu, Yaochen Sheng, Jingyi Ma, Junyan Ren, Wenzhong Bao
2019	J	`jnl`	3D FEM Analysis of High-Frequency AlN-Based PMUT Arrays on Cavity SOI. Sensors Wenjuan Liu, Leming He, Xubo Wang, Jia Zhou, Weijiang Xu, Nikolay Smagin, Malika Toubal, Hao Yu, Yuandong Gu, Jinghui Xu, Denis Remiens, Junyan Ren
2019	—	`conf`	A 10b 250MS/s SAR ADC with Speed-Enhanced SAR Logic and Free Time More Than a Half of Sampling Period. ASICON Shumin Zhang, Yuefeng Cao, Fan Ye, Junyan Ren
2019	C	`conf`	A 13-bit 180-MS/s SAR ADC with Efficient Capacitor-Mismatch Estimation and Dither Enhancement. ISCAS Fan Ye, Shuai Li, Min Zhu, Zhekan Ni, Junyan Ren
2019	—	`conf`	A 130-150 GHz Power Amplifier for Millimeter Wave Imaging in 65-nm CMOS. ASICON Jincheng Zhang, Lihe Nie, Dong Wei, Tianxiang Wu, Shunli Ma, Junyan Ren
2019	—	`conf`	A 140 GHz, 4 dB Noise-Figure Low-Noise Amplifier Design with the Compensation of Parasitic Capacitance CGS. MWSCAS Dong Wei, Xuan Ding, Hai Yu, Bo Yu, Shunli Ma, Qun Jane Gu, Junyan Ren
2019	—	`conf`	A 20MHz Bandwidth Band-Pass Noise-Shaping SAR ADC With OPAMP Sharing Switched-Capacitor Filter. MWSCAS Shuai Li, Jianguo Diao, Yimin Wu, Fan Ye, Junyan Ren
2019	—	`conf`	A 22-40.5 GHz UWB LNA Design in 0.15um GaAs. ASICON Dong Wei, Jincheng Zhang, Tianxiang Wu, Shunli Ma, Junyan Ren
2019	—	`conf`	A 256MHz Analog Baseband Chain with tunable Bandwidth and Gain for UWB Receivers. ASICON Yuting Yao, Jipeng Wei, Manxin Li, Shunli Ma, Fan Ye, Junyan Ren
2019	—	`conf`	A 36-40 GHz VCO with bonding inductors for millimeter wave 5G Communication. ASICON Tianxiang Wu, Jincheng Zhang, Dong Wei, Lihe Nie, Yuting Yao, Shunli Ma, Junyan Ren
2019	—	`conf`	A 40Gb/s Low Power Transmitter with 2-tap FFE and 40: 1 MUX in 28nm CMOS Technology. ASICON Wenbin He, Fan Ye, Junyan Ren
2019	J	`jnl`	A 5-10-Gb/s 12.5-mW Source Synchronous I/O Interface With 3-D Flip Chip Package. IEEE Trans. Circuits Syst. I Regul. Pap. Shunli Ma, Hao Yu, Qun Jane Gu, Junyan Ren
2019	—	`conf`	A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps. ESSCIRC Yongzhen Chen, Xingchen Shen, Zhekan Ni, Jingchao Lan, Chixiao Chen, Fan Ye, Junyan Ren
2019	J	`jnl`	A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic. Microelectron. J. Zhekan Ni, Yongzhen Chen, Fan Ye, Junyan Ren
2019	—	`conf`	A Band-Pass Noise-Shaping Modulator Using the Error-Feedback Structure on a 10-bit SAR ADC. MWSCAS Longheng Luo, Shuai Li, Jipeng Wei, Yimin Wu, Fan Ye, Junyan Ren
2019	C	`conf`	A Capacitively-Degenerated High-Linearity Dynamic Amplifier using a Real-Time Gain Detection Technique. ISCAS Longheng Luo, Yimin Wu, Jipeng Wei, Fan Ye, Junyan Ren
2019	—	`conf`	A Comparator-Reused Dynamic-Amplifier for Noise-Shaping SAR ADC. ASICON Longheng Luo, Xingchen Shen, Jianguo Diao, Fan Ye, Junyan Ren
2019	C	`conf`	A Novel Nauta Transconductor for Ultra-Wideband gm-C Filter with Temperature Calibration. ISCAS Jipeng Wei, Yuting Yao, Longheng Luo, Shunli Ma, Fan Ye, Junyan Ren
2019	—	`conf`	A Ring Amplifier Based Current Feedback Continuous Time PGA for High Frequency Ultrasound Applications. MWSCAS Yimin Wu, Jingchao Lan, Shuai Li, Fan Ye, Junyan Ren
2019	—	`conf`	Energy-Efficient Analog Frond-End Design for Ultrasound Imaging Applications. MWSCAS Jianguo Diao, Shuai Li, Yimin Wu, Fan Ye, Jun Xu, Junyan Ren
2019	—	`conf`	Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR. ESSCIRC Tianli Zhang, Yuefeng Cao, Shumin Zhang, Chixiao Chen, Fan Ye, Junyan Ren
2019	—	`conf`	SPICE Modeling and Simulation of High-Performance Wafer-Scale MoS2 Transistors. ASICON Yuting Yao, Manxin Li, Tianxiang Wu, Hu Xu, Shunli Ma, Wenzhong Bao, Junyan Ren
2018	C	`conf`	A 100MS/S 12-bit Coarse-Fine SAR ADC with Shared Split-CDAC. ISCAS Manxin Li, Yongzhen Chen, Fan Ye, Junyan Ren
2018	—	`conf`	A 12-Bit ENOB 8MHz BW Noise-Shaping SAR ADC Using High-Speed Switches. MWSCAS Zhiyuan Dai, Hang Hu, Yongzhen Chen, Fan Ye, Junyan Ren
2018	J	`jnl`	A 5-to-8-GHz Wideband Miniaturized Dielectric Spectroscopy Chip With $I/Q$ Mismatch Calibration in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Shunli Ma, Ning Li, Junyan Ren
2018	—	`conf`	A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic. APCCAS Zhekan Ni, Yongzhen Chen, Fan Ye, Junyan Ren
2018	C	`conf`	A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation. ISCAS Yongzhen Chen, Zhekan Ni, Yuefeng Cao, Fan Ye, Junyan Ren
2018	—	`conf`	A Third-order Band-pass Fully-passive Noise-Shaping Modulator Based on a Time-interleaved SAR ADC. MWSCAS Zhiyuan Dai, Hang Hu, Yimin Wu, Fan Ye, Junyan Ren
2018	J	`jnl`	A Time-Interleaved SAR Assisted Pipeline ADC With a Bias-Enhanced Ring Amplifier. IEEE Trans. Circuits Syst. II Express Briefs Yongzhen Chen, Jingjing Wang, Hang Hu, Fan Ye, Junyan Ren
2018	—	`conf`	An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC. APCCAS Yuefeng Cao, Yongzhen Chen, Zhekan Ni, Fan Ye, Junyan Ren
2018	J	`jnl`	An 8.2 fJ/conversion-step 9-bit 135 MS/s SAR ADC with redundant methods for acceleration. Microelectron. J. Yongzhen Chen, Fan Ye, Junyan Ren
2018	C	`conf`	An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs. ISCAS Yuefeng Cao, Tianli Zhang, Yongzhen Chen, Fan Ye, Junyan Ren
2018	—	`conf`	Low Power Low Noise Amplifier with DC Offset Correction at 1 V Supply Voltage for Ultrasound Imaging Systems. MWSCAS Longheng Luo, Yimin Wu, Jianguo Diao, Fan Ye, Junyan Ren
2018	C	`conf`	Use Multilayer Perceptron in Calibrating Multistage Non-linearity of Split Pipelined-ADC. ISCAS Tianli Zhang, Yuefeng Cao, Fan Ye, Junyan Ren
2017	—	`conf`	A 0.87 mW 7MHz-BW 76dB-SNDR passive noise-shaping modulator based on a SAR ADC. ASICON Zhiyuan Dai, Hang Hu, Manxin Li, Fan Ye, Junyan Ren
2017	—	`conf`	A 12bit asynchronous SAR-incremental sub-range ADC. ASICON Manxin Li, Hang Hu, Zhiyuan Dai, Fan Ye, Junyan Ren
2017	—	`conf`	A 13-bit non-binary weighted SAR ADC with bridge structure using digital calibration for capacitor weight error. ASICON Xiaoqing Chen, Fan Ye, Junyan Ren
2017	—	`conf`	A 15MHz BW continuous-time ΔΣ modulator with high speed digital ELD compensation. ASICON Hang Hu, Manxin Li, Zhiyuan Dai, Fan Ye, Junyan Ren
2017	C	`conf`	A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier. ISCAS Yongzhen Chen, Jingjing Wang, Hang Hu, Fan Ye, Junyan Ren
2017	—	`conf`	A 320MS/s 7-b flash-SAR ADC with preamplifier sharing technique. ASICON Hang Hu, Zhiyuan Dai, Manxin Li, Fan Ye, Junyan Ren
2017	—	`conf`	A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOS. A-SSCC Shunli Ma, Jili Sheng, Ning Li, Junyan Ren
2017	—	`conf`	A background time-skew calibration technique in flash-assisted time-interleaved SAR ADCs. ASICON Yongzhen Chen, Yimin Wu, Fubiao Cao, Fan Ye, Junyan Ren
2017	—	`conf`	A proved dither-injection method for memory effect in double sampling pipelined ADC. ASICON Fubiao Cao, Yongzhen Chen, Yuefeng Cao, Fan Ye, Junyan Ren
2017	—	`conf`	A stacked-packaged 16-channel ADC for ultrasound application. ASICON Yimin Wu, Yongzhen Chen, Manxin Li, Fan Ye, Junyan Ren
2017	—	`conf`	An improved ring amplifier with process- and supply voltage-insensitive dead-zone. MWSCAS Yuefeng Cao, Yongzhen Chen, Tianli Zhang, Fan Ye, Junyan Ren
2017	—	`conf`	An input buffer for 12bit 2GS/s ADC. ASICON Fubiao Cao, Yongzhen Chen, Zhiyuan Dai, Fan Ye, Junyan Ren
2017	—	`conf`	High speed digital ELD compensation with hybrid thermometer coding in CT ΔΣ modulators. MWSCAS Hang Hu, Zemin Feng, Chixiao Chen, Fan Ye, Junyan Ren
2017	J	`jnl`	Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching. IEEE Trans. Very Large Scale Integr. Syst. Dezhi Xing, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, Rui Paulo Martins
2016	—	`conf`	A 7.9-GHz transformer-feedback quadrature VCO with a noise-shifting coupling network. A-SSCC Bingwei Jiang, Chixiao Chen, Junyan Ren, Howard C. Luong
2016	—	`conf`	Transformer-based varactor-less 96GHz-110GHz VCO and 89GHz-101GHz QVCO in 65nm CMOS. A-SSCC Xiaolong Liu, Chixiao Chen, Junyan Ren, Howard C. Luong
2015	—	`conf`	100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array. ASICON Jingjing Wang, Rongjin Xu, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren
2015	—	`conf`	A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network. ASICON Rongjin Xu, Yongzhen Chen, Mingshuo Wang, Ning Li, Fan Ye, Junyan Ren
2015	—	`conf`	A 100MS/s 5bit fully digital flash ADC with standard cells. ASICON Xiangyan Xue, Xuerong Zhou, Fan Ye, Junyan Ren
2015	—	`conf`	A 20MHz BW 35fJ/conv. continuous-time ΣΔ modulator with single-opamp resonator using finite GBW compensation method. ASICON Zemin Feng, Jingjing Wang, Chixiao Chen, Jun Xu, Junyan Ren
2015	J	`jnl`	A 270-MS/s 6-b SAR ADC with preamplifier sharing and self-locking comparators. IEICE Electron. Express Chixiao Chen, Jixuan Xiang, Jiang Fan, Xu Jun, Ye Fan, Junyan Ren
2015	—	`conf`	A 30-GHz to 39-GHz mm-Wave low-power injection-locked frequency divider in 65nm CMOS. ASICON Guangyao Zhou, Shunli Ma, Fazhi An, Ning Li, Fan Ye, Junyan Ren
2015	—	`conf`	A 39 GHz-80 GHz millimeter-wave frequency doubler with low power consumption in 65nm CMOS tehnology. ASICON Qian Chen, Fazhi An, Guangyao Zhou, Shunli Ma, Fan Ye, Junyan Ren
2015	J	`jnl`	A Monolithic Sub-sampling PLL based 6-18 GHz Frequency Synthesizer for C, X, Ku Band Communication. IEICE Trans. Electron. Hanchao Zhou, Ning Zhu, Wei Li, Zibo Zhou, Ning Li, Junyan Ren
2015	J	`jnl`	A high power-efficient LVDS output driver with adjustable feed-forward capacitor compensation. IEICE Electron. Express Yuan Su, Fan Ye, Junyan Ren
2015	—	`conf`	A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system. ESSCIRC Shunli Ma, Guangyao Zhou, Jianbing Jiang, Chixiao Chen, Yongzhen Chen, Fan Ye, Junyan Ren
2015	—	`conf`	A wide-division-ratio 100MHz-to-5GHz multi-modulus divider chain for wide-band PLL. ASICON Fazhi An, Shunli Ma, Qian Chen, Guangyao Zhou, Fan Ye, Junyan Ren
2015	—	`conf`	An 8-bit 4fs-step digitally controlled delay element with two cascaded delay units. ASICON Weizhen Wang, Hao Zhou, Fan Ye, Junyan Ren
2015	J	`jnl`	An ARMA-Model-Based NTF Estimation on Continuous-Time ΔΣ Modulators. IEEE Trans. Circuits Syst. II Express Briefs Chixiao Chen, Zemin Feng, Jun Xu, Fan Ye, Junyan Ren
2015	J	`jnl`	Greedy Approach Based Heuristics for Partitioning Sparse Matrices. IEICE Trans. Inf. Syst. Jiasen Huang, Junyan Ren, Wei Li
2015	B	`conf`	Greedy approach based heuristics for partitioning SpMxV on FPGAs. FPL Jiasen Huang, Weina Lu, Junyan Ren
2015	—	`conf`	I/Q imbalance estimation in OFDM systems. ASICON Xuerong Zhou, Xiangyan Xue, Fan Ye, Junyan Ren
2015	—	`conf`	LVDS transmitter with optimized high power-efficiency 8: 1 MUX. ASICON Yuan Su, Yimin Wu, Qiang Zhang, Xuerong Zhou, Fan Ye, Junyan Ren
2015	J	`jnl`	Switch-back based on charge equalization switching technique for SAR ADC. IEICE Electron. Express Weiru Gu, Fan Ye, Junyan Ren
2014	—	`conf`	A 131.5GHz, -84dBm sensitivity super-regenerative receiver by zero-phase-shifter coupled oscillator network in 65nm CMOS. ESSCIRC Shunli Ma, Hao Yu, Yang Shang, Wei Meng Lim, Junyan Ren
2014	C	`conf`	A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators. ISCAS Guoxian Dai, Chixiao Chen, Shunli Ma, Fan Ye, Junyan Ren
2014	J	`jnl`	A 42fJ 8-bit 1.0-GS/s folding and interpolating ADC with 1GHz signal bandwidth. IEICE Electron. Express Mingshuo Wang, Fan Ye, Wei Li, Junyan Ren
2014	J	`jnl`	A 7 bit 1 GS/s pipelined folding and interpolating ADC with IEICE Electron. Express Mingshuo Wang, Li Lin, Fan Ye, Junyan Ren
2014	C	`conf`	A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier. ISCAS Chixiao Chen, Zemin Feng, Huabin Chen, Mingshuo Wang, Jun Xu, Fan Ye, Junyan Ren
2014	—	`conf`	An overview of new design techniques for high performance CMOS millimeter-wave circuits. ISIC Shunli Ma, Junyan Ren, Hao Yu
2014	J	`jnl`	Design and Analysis of Wide Frequency-Tuning-Range CMOS 60 GHz VCO by Switching Inductor Loaded Transformer. IEEE Trans. Circuits Syst. I Regul. Pap. Wei Fei, Hao Yu, Haipeng Fu, Junyan Ren, Kiat Seng Yeo
2014	—	`conf`	General expression based inner loop unrolling scheme for TV-GD algorithm adopted in photoacoustic imaging. BioCAS Jiasen Huang, Junyan Ren, Jun Xu, Yuanyuan Wang
2014	—	`conf`	No zero padded sparse matrix-vector multiplication on FPGAs. FPT Jiasen Huang, Junyan Ren, Wenbo Yin, Lingli Wang
2013	J	`jnl`	A 0.13-µm CMOS 0.1-12GHz active balun-LNA for multi-standard applications. IEICE Electron. Express Kaichen Zhang, Wei Li, Ning Li, Junyan Ren
2013	—	`conf`	A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique. ASICON Yongzhen Chen, Chixiao Chen, Qiang Zhang, Fan Ye, Junyan Ren
2013	—	`conf`	A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC. ASICON Jian Mei, Jixuan Xiang, Huabin Chen, Fan Ye, Junyan Ren
2013	—	`conf`	A 75.7GHz to 102GHz rotary-traveling-wave VCO by tunable composite right /left hand T-line. CICC Shunli Ma, Wei Fei, Hao Yu, Junyan Ren
2013	—	`conf`	A 80-dB DR, 10-MHz BW continuous-time sigma-delta modulator with low power comparators and switch drivers. ASICON Yuzhong Xiao, Chixiao Chen, Rui Wei, Fan Jiang, Jun Xu, Junyan Ren
2013	J	`jnl`	A 96-GHz Oscillator by High-Q Differential Transmission Line loaded with Complementary Split-Ring Resonator in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Wei Fei, Hao Yu, Yang Shang, Deyun Cai, Junyan Ren
2013	—	`conf`	A DLL based low-phase-noise clock multiplier with offset-tolerant PFD. ASICON Yuwen Wang, Fan Ye, Junyan Ren
2013	J	`jnl`	A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter. IEEE Trans. Circuits Syst. I Regul. Pap. Deyun Cai, Haipeng Fu, Junyan Ren, Wei Li, Ning Li, Hao Yu, Kiat Seng Yeo
2013	J	`jnl`	A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1. IEEE Trans. Circuits Syst. I Regul. Pap. Zhenyu Wang, Mingshuo Wang, Weiru Gu, Chixiao Chen, Fan Ye, Junyan Ren
2013	—	`conf`	A finite gain bandwidth compensation method for low power continuous-time ΣΔ modulator. ASICON Zemin Feng, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren
2013	J	`jnl`	A mixed sample-time error calibration technique in time-interleaved ADCs. IEICE Electron. Express Bei Yu, Chixiao Chen, Fan Ye, Junyan Ren
2013	—	`conf`	A novel joint estimation and compensation algorithm for non-idealities of analog front-end in DC-OFDM system. ASICON Jiasen Huang, Hao Chen, Junyan Ren, Fan Ye
2013	—	`conf`	Automatic gain control algorithm with high-speed and double closed-loop in UWB system. ASICON Bing Jing, Yuankun Xue, Fan Ye, Ning Li, Junyan Ren
2013	—	`conf`	Beyond-one-cycle loop delay CT ΔΣ modulators with proper rational NTF synthesis and time-interleaved quantizers. MWSCAS Fan Jiang, Chixiao Chen, Yuzhong Xiao, Jun Xu, Junyan Ren
2013	J	`jnl`	Carrier Frequency Offset and I/Q Imbalance Compensation for MB-OFDM Based UWB System. Wirel. Pers. Commun. Liang Liu, Junyan Ren, Jun Zhou, Fan Ye
2013	—	`conf`	FFT design for OFDM-based cognitive radio using a reconfigurable baseband processing architecture. ASICON Wenqing Lu, Gerald E. Sobelman, Xiaofang Zhou, Junyan Ren
2013	—	`conf`	Low-complexity synchronizer used in DC-OFDM UWB system. ASICON Bing Jing, Hao Chen, Fan Ye, Ning Li, Junyan Ren
2013	—	`conf`	Power efficient SAR ADC with optimized settling technique. MWSCAS Weiru Gu, Hao Zhou, Tao Lin, Zhenyu Wang, Fan Ye, Junyan Ren
2012	—	`conf`	A 1.2 V 1.0-GS/s 8-bit Voltage-Buffer-Free Folding and interpolating ADC. MWSCAS Mingshuo Wang, Tao Lin, Fan Ye, Ning Li, Junyan Ren
2012	J	`jnl`	A 2.4GHz to 3.86GHz digitally controlled oscillator with 18.5kHz frequency resolution using single PMOS varactor. IEICE Electron. Express Yangyang Niu, Wei Li, Ning Li, Junyan Ren
2012	J	`jnl`	A Fast Non-Monte-Carlo Yield Analysis and Optimization by Stochastic Orthogonal Polynomials. ACM Trans. Design Autom. Electr. Syst. Fang Gong, Xuexin Liu, Hao Yu, Sheldon X.-D. Tan, Junyan Ren, Lei He
2012	—	`conf`	A cancellation technique for output-dependent delay differences in high-accuracy DACs. MWSCAS Long Cheng, Yu-Jing Lin, Mingshuo Wang, Fan Ye, Ning Li, Junyan Ren
2012	—	`conf`	A digitally calibrated current-steering DAC with current-splitting array. MWSCAS Long Cheng, Chixiao Chen, Fan Ye, Ning Li, Junyan Ren
2012	—	`conf`	A low power programmable band-pass filter with novel pseudo-resistor for portable biopotential acquisition system. APCCAS Shunli Ma, Changming Chen, Yiwen Zhang, Junyan Ren
2012	—	`conf`	A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation. APCCAS Yiwen Zhang, Xiaoshi Zhu, Chixiao Chen, Fan Ye, Junyan Ren
2012	C	`conf`	A time-to-digital converter based AFC for wideband frequency synthesizer. ISCAS Deping Huang, Wei Li, Jin Zhou, Ning Li, Junyan Ren, Jinghong Chen
2012	—	`conf`	An 8-bit 100-MS/s Digital-to-Skew Converter with 200-ps range for time-interleaved sampling. MWSCAS Chixiao Chen, Shengchang Cai, Jialiang Xu, Xiaoshi Zhu, Fan Ye, Junyan Ren
2012	—	`conf`	Carrier Frequency Offset estimation in the Presence of I/Q Mismatch for Wideband OFDM systems. MWSCAS Xiaolong Wang, Yuankun Xue, Liang Liu, Fan Ye, Junyan Ren
2012	J	`jnl`	Comments on "Estimation of Carrier Frequency Offset With I/Q Mismatch Using Pseudo-Offset Injection in OFDM Systems". IEEE Trans. Circuits Syst. I Regul. Pap. Xiaolong Wang, Fan Ye, Junyan Ren
2012	C	`conf`	Output-dependent delay cancellation technique for high-accuracy current-steering DACs. ISCAS Long Cheng, Yu-Jing Lin, Fan Ye, Ning Li, Junyan Ren
2011	—	`conf`	A 1.2 V 70 mA low drop-out voltage regulator in 0.13 µm CMOS process. ASICON Qin Wu, Wei Li, Ning Li, Junyan Ren
2011	—	`conf`	A 12-bit 50-MSPS SHA-less opamp-sharing Analog-to-Digital converter in 65nm CMOS. ASICON Chen Shu, Guanghua Shu, Jun Xu, Fan Ye, Junyan Ren
2011	—	`conf`	A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation. A-SSCC Bei Yu, Chixiao Chen, Yu Zhu, Peng Zhang, Yiwen Zhang, Xiaoshi Zhu, Fan Ye, Junyan Ren
2011	—	`conf`	A 2.1-GHz PLL with -80dBc/-74dBc reference spur based on aperture-phase detector and phase-to-analog converter. A-SSCC Deyun Cai, Haipeng Fu, Junyan Ren, Wei Li, Ning Li, Hao Yu, Kiat Seng Yeo
2011	J	`jnl`	A 22-mW 2.2%-EVM UWB Transmitter Using On-Chip Transformer and LO Leakage Calibration. IEICE Trans. Electron. Yunfeng Chen, Renliang Zheng, Haipeng Fu, Wei Li, Ning Li, Junyan Ren
2011	—	`conf`	A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded application. ASICON Qianqian Ha, Fan Ye, Chixiao Chen, Xiaoshi Zhu, Mingshuo Wang, Yu-Jing Lin, Ning Li, Junyan Ren
2011	J	`jnl`	A 5.5mW 80-400MHz Gm-C low pass filter with a unique auto-tuning system. IEICE Electron. Express Ting Gao, Wei Li, Yunfeng Chen, Ning Li, Junyan Ren
2011	J	`jnl`	A 6.2-9.5 GHz receiver for Wimedia MB-OFDM and China UWB standard. Sci. China Inf. Sci. Ting Gao, Feng Zhou, Wei Li, Fei Lan, Ning Li, Junyan Ren
2011	—	`conf`	A 80-400 MHz 74 dB-DR Gm-C low-pass filter with a unique auto-tuning system. ASP-DAC Ting Gao, Wei Li, Ning Li, Junyan Ren
2011	J	`jnl`	A Parallel Early-Pruned K-Best MIMO Signal Detector Up to 1.9Gb/s. Wirel. Pers. Commun. Liang Liu, Junyan Ren, Xiaojing Ma, Fan Ye
2011	J	`jnl`	A current-mode RF transmitter for 6-9 GHz MB-OFDM UWB application. Sci. China Inf. Sci. Yunfeng Chen, Jinhan Fan, Wei Li, Ning Li, Junyan Ren
2011	C	`conf`	A dual-mode VCO based low-power synthesizer with optimized automatic frequency calibration for software-defined radio. ISCAS Jin Zhou, Wei Li, Deping Huang, Chen Lian, Ning Li, Junyan Ren
2011	C	`conf`	A harmonic-suppressed regenerative divide-by-5 frequency divider for UWB applications. ISCAS Haipeng Fu, Deyun Cai, Junyan Ren, Wei Li
2011	—	`conf`	A low-voltage differential injection locked divider with forward body bias. ASICON Haipeng Fu, Hanchao Zhou, Yangyang Niu, Junyan Ren, Wei Li, Ning Li
2011	—	`conf`	Area efficient LDPC decoder design for parallel layered decoding. ASICON Yuan Yao, Fan Ye, Junyan Ren
2011	—	`conf`	Class-AB CMOS buffer with floating class-AB control. ASICON Peng Zhang, Fan Ye, Junyan Ren
2011	—	`conf`	Low phase noise injection-locked doubler-based quadrature CMOS VCO. ASICON Chen Lian, Wei Li, Haipeng Fu, Ning Li, Junyan Ren
2011	C	`conf`	Nyquist-rate time-interleaved current-steering DAC with dynamic channel matching. ISCAS Long Cheng, Fan Ye, Hai-Feng Yang, Ning Li, Jun Xu, Junyan Ren
2011	J	`jnl`	Reconfigurable baseband processing architecture for communication. IET Comput. Digit. Tech. Wenqing Lu, Shuang Zhao, Xiaofang Zhou, Junyan Ren, Gerald E. Sobelman
2010	C	`conf`	A 0.22 pJ/step subsampling ADC with fast input-tracking sampling and simplified opamp sharing. ISCAS Guanghua Shu, Fan Ye, Yao Guo, Mingjun Fan, Junyan Ren, Jun Xu, Ning Li, Cheng Chen
2010	J	`jnl`	A 1.1-Gb/s 115-pJ/bit Configurable MIMO Detector Using 0.13- muhboxm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs Liang Liu, Fan Ye, Xiaojing Ma, Tong Zhang, Junyan Ren
2010	C	`conf`	A current-mode 6-9GHz UWB transmitter with output power flattening technique. ISCAS Yunfeng Chen, Jinhan Fan, Wei Li, Ning Li, Junyan Ren
2010	C	`conf`	A fractional-N frequency synthesizer for cellular and short range multi-standard wireless receiver. ISCAS Deping Huang, Jin Zhou, Wei Li, Ning Li, Junyan Ren
2010	C	`conf`	A sideband-suppressed low-power synthesizer for 14-band dual-carrier MB-OFDM UWB transceivers. ISCAS Danfeng Chen, Haipeng Fu, Yunfeng Chen, Wei Li, Fan Ye, Ning Li, Junyan Ren
2010	C	`conf`	Joint estimation and compensation for front-end imperfection in MB-OFDM UWB systems. ISCAS Jun Zhou, Liang Liu, Fan Ye, Junyan Ren
2010	A*	`conf`	QuickYield: an efficient global-search based parametric yield estimation with performance constraints. DAC Fang Gong, Hao Yu, Yiyu Shi, DaeSoo Kim, Junyan Ren, Lei He
2009	—	`conf`	A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator. SoCC Ping Lu, Danfeng Chen, Fan Ye, Junyan Ren
2009	C	`conf`	A Low Power Low Voltage 16 Bit Audio SigmaDelta Modulator. ISCAS Xi Gou, Yiran Li, Jian-qiu Chen, Jun Xu, Junyan Ren
2009	C	`conf`	A Novel Operational Amplifier for Low-voltage Low-power SC Circuits. ISCAS Mingjun Fan, Junyan Ren, Yao Guo, Yuanwen Li, Fan Ye, Ning Li
2009	—	`conf`	A digitally calibrated 14-bit linear 100-MS/s pipelined ADC with wideband sampling frontend. ESSCIRC Lei Luo, Kaihui Lin, Long Cheng, Liren Zhou, Fan Ye, Junyan Ren
2008	—	`conf`	Design of Highly-Parallel, 2.2Gbps Throughput Signal Detector for MIMO Systems. ICC Liang Liu, Xiaojing Ma, Fan Ye, Junyan Ren
2007	C	`conf`	A High-Speed High-Resolution Low-Distortion CMOS Bootstrapped Switch. ISCAS Lei Wang, Junyan Ren, Wenjing Yin, Tingqian Chen, Jun Xu
2007	B	`conf`	A Novel Synchronizer for OFDM-based UWB System on New Preamble Design. PIMRC Xuejing Wang, Liang Liu, Fan Ye, Junyan Ren, Bo Hu
2007	C	`conf`	A Power-Optimized CMOS Quadrature VCO with Wide-Tuning Range for UWB Receivers. ISCAS Zhujin Zhou, Ning Li, Wei Li, Junyan Ren
2007	C	`conf`	Design of Low-Power, 1GS/s Throughput FFT Processor for MIMO-OFDM UWB Communication System. ISCAS Liang Liu, Junyan Ren, Xuejing Wang, Fan Ye
2007	C	`conf`	Implementation of Folded Sliding Block Viterbi Decoders for MB-OFDM UWB Communication System. ISCAS Zhuo Xu, Junyan Ren, Xuejing Wang, Fan Ye
2006	C	`conf`	A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet. ISCAS Lu Ping, Ye Fan, Junyan Ren
2006	—	`conf`	An implementation of a CMOS down-conversion mixer for GSM1900 receiver. ASP-DAC Fangqing Chu, Wei Li, Junyan Ren
2003	—	`conf`	Periodic steady-state analysis of coupled ODE-AE-CGE systems for MOS RF autonomous circuit simulation. ASP-DAC Xinyu Wu, Zaiman Chen, Jinmei Lai, Qianling Zhang, Omar Wing, Junyan Ren
2002	—	`conf`	Iterative solution of ODE-PDE-AE systems for RF circuit simulation. ISCAS (4) Omar Wing, Tan Jun, Jinmei Lai, Junyan Ren, Qianling Zhang