Junji Ogawa

19 papers Journal 12Unranked 7
YearRankTypeTitle / Venue / Authors
2010 J jnl
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS.
IEEE J. Solid State Circuits
Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker
2010 J jnl
A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS.
IEEE J. Solid State Circuits
Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Junji Ogawa
2010 — conf
A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS.
ISSCC
Hisakatsu Yamaguchi, Hirotaka Tamura, Yoshiyasu Doi, Yasumoto Tomita, Takayuki Hamada, Masaya Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, Ali Sheikholeslami, Tomokazu Higuchi, Junji Ogawa, Tamio Saito, Hideki Ishida, Kohtaroh Gotoh
2010 J jnl
Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC.
IEICE Trans. Electron.
Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda
2009 J jnl
A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS.
IEEE J. Solid State Circuits
Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker
2009 — conf
A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS.
ISSCC
Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker
2009 — conf
Split capacitor DAC mismatch calibration in successive approximation ADC.
CICC
Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda
2008 J jnl
20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range.
IEEE J. Solid State Circuits
Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda
2007 J jnl
18-GHz Clock Distribution Using a Coupled VCO Array.
IEICE Trans. Electron.
Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda
2007 J jnl
A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS.
IEEE J. Solid State Circuits
Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda
2007 J jnl
A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX.
IEEE J. Solid State Circuits
Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker
2007 — conf
A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX.
ISSCC
Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker
2006 — conf
A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid.
ISSCC
Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda
2006 J jnl
Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies.
IEICE Trans. Electron.
Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Kouichi Kanda, Kohtaroh Gotoh, Hideki Ishida, Junji Ogawa
2005 — conf
A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process.
CICC
Yoshiyasu Doi, Syunitirou Masaki, Takaya Chiba, Hirohito Higashi, Hisakatsu Yamaguchi, Hideki Takauchi, Hideki Ishida, Kohtaroh Gotoh, Junji Ogawa, Hirotaka Tamura
2005 J jnl
A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS.
IEEE J. Solid State Circuits
Yasumoto Tomita, Masaya Kibune, Junji Ogawa, William W. Walker, Hirotaka Tamura, Tadahiro Kuroda
2005 J jnl
A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique.
IEEE J. Solid State Circuits
Yusuke Okaniwa, Hirotaka Tamura, Masaya Kibune, Daisuke Yamazaki, Tsz-Shing Cheung, Junji Ogawa, Nestoras Tzartzanis, William W. Walker, Tadahiro Kuroda
2000 — conf
A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro.
Intelligent Memory Systems
Junji Ogawa, Mark Horowitz
1998 J jnl
500-Mb/s nonprecharged data bus for high-speed DRAM's.
IEEE J. Solid State Circuits
Miyoshi Saito, Junji Ogawa, Hirotaka Tamura, Shigetoshi Wakayama, Hisakatsu Araki, Tsz-Shing Cheung, Kohtaroh Gotoh, Tadao Aikawa, Takaaki Suzuki, Masao Taguchi, Takeshi Imamura