Junichi Hirase

16 papers A 2Journal 3Unranked 11

Year	Rank	Type	Title / Venue / Authors
2014	J	`jnl`	Introduction of Yield Quadrant and Yield Capability Index for VLSI Manufacturing. IEICE Trans. Electron. Junichi Hirase
2014	J	`jnl`	Verification of Moore's Law Using Actual Semiconductor Production Data. IEICE Trans. Electron. Junichi Hirase
2008	—	`conf`	Defect Detection Rate through IDDQ for Production Testing. ATS Junichi Hirase
2005	—	`conf`	Chip Identification using the Characteristic Dispersion of Transistor. Asian Test Symposium Junichi Hirase, Tatsuya Furukawa
2005	—	`conf`	IDDQ Testing Method using a Scan Pattern for Production Testing. Asian Test Symposium Junichi Hirase, Yoshiyuki Goi, Yoshiyuki Tanaka
2003	—	`conf`	Test Pattern Length Required to Reach the Desired Fault Coverage. Asian Test Symposium Junichi Hirase
2002	—	`conf`	High Precision Result Evaluation of VLSI. Asian Test Symposium Junichi Hirase
2001	—	`conf`	Test Time Reduction through Minimum Execution of Tester-Hardware Setting Instructions. Asian Test Symposium Junichi Hirase
2001	—	`conf`	Yield Increase of VLSI after Redundancy-Repairing. Asian Test Symposium Junichi Hirase
2000	—	`conf`	Faster processing for microprocessor functional ATPG. Asian Test Symposium Junichi Hirase, Shinichi Yoshimura
1999	—	`conf`	Automatic Test Pattern Generation for Improving the Fault Coverage of Microprocessors. Asian Test Symposium Junichi Hirase, Shinichi Yoshimura, Tomohisa Sczaki
1999	—	`conf`	Scan Chain Diagnosis Using IDDQ Current Measurement. Asian Test Symposium Junichi Hirase, Naoki Shindou, Kouji Akahori
1998	—	`conf`	Economical Importance of the Maximum Chip Area. Asian Test Symposium Junichi Hirase
1995	A	`conf`	Improvement of the Defect Level of Micro-computer LSI Testing. ITC Junichi Hirase
1995	A	`conf`	Study on the Costs of On-site VLSI Testing. ITC Junichi Hirase
1995	J	`jnl`	The Effect of CMOS VLSI IDDq Measurement on Defect Level. IEICE Trans. Inf. Syst. Junichi Hirase, Masanori Hamada