Jun Yin - RankMe

90 papers C 3Journal 55Unranked 32

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	27.5 A $17.9-\text{to}-22.4 \text{GHz} 195.6 \pm 1.3 \text{dBc} / \text{Hz}$ FoM Quad-Core Class-F Class-F ISSCC Yue Wu, Yatao Peng, Jiawei Li, Fengen Yuan, Jinge Li, Jun Yin, Rui Paulo Martins, Pui-In Mak
2026	—	`conf`	27.9 A Dual-Mode DCO-PA with a Twisted 8-Shape Inductor for BLE Achieving 42% TX Efficiency at 1.6dBm and 0.29mW RX Clock. ISSCC Jiawen Chen, Kai Xu, Luyi Guo, Teerachot Siriburanon, Jun Yin, Bashir M. Al-Hashimi, Robert Bogdan Staszewski
2026	—	`conf`	A 0.068mm ISSCC Xincheng Du, Xiangxun Zhan, Tincheng Ou, Zaize Chen, Jinge Li, Haoran Li, Zhizhan Yang, Zhuo Xu, Pui-In Mak, Rui Paulo Martins, Jun Yin
2026	—	`conf`	A Compact Dual-Capacitor Relay SPT Supply Modulator with Overshoot-Free Adaptive on-Time Control for 5G FR2 CMOS PA. ISSCC Zhewen Yu, Zhiguo Tong, Junwei Huang, Jun Yin, Yan Lu
2026	J	`jnl`	A Low Phase Noise and High-Efficiency Biharmonic Class-F IEEE J. Solid State Circuits Yue Wu, Yatao Peng, Jun Yin, Rui Paulo Martins, Pui-In Mak
2025	—	`conf`	19.7 A 27GHz Fractional-N Sub-Sampling PLL Achieving 57.9fs ISSCC Haoran Li, Jinge Li, Xueying Jiang, Xi Meng, Jun Yin, Rui Paulo Martins, Pui-In Mak
2025	J	`jnl`	A 0.0019-mm² LC-Ring Oscillator With an Ultra-Compact Transformer Achieving 175.2 dBc/Hz FoM@1MHz and 202.4 dBc/Hz FoMA. IEEE Trans. Circuits Syst. II Express Briefs Ya Zhao, Lingao Huang, Runchen Wang, Jun Yin, Pui-In Mak, Li Geng, Chao Fan
2025	—	`conf`	A 0.4μW/MHz Reference-Replication-Based RC Oscillator with Path-Delay and Comparator-Offset Cancellation Achieving 9.83ppm/°C from -40 to 125°C. ISSCC Yueduo Liu, Zihao Zhu, Xinyu Yang, Rongxin Bao, Zehao Zhang, Hongshuai Zhang, Jiaxin Liu, Zheng Wang, Mingkang Zhang, Na Yan, Jun Yin, Pui-In Mak, Shiheng Yang
2025	C	`conf`	A 0.6V Digital-intensive Pulse Injection 32-kHz Crystal Oscillator Using Stacked Logic Gates. ISCAS Zhizhan Yang, Jun Yin, Rui Paulo Martins, Pui-In Mak
2025	J	`jnl`	A 90.7-nW Vibration-Based Condition Monitoring Chip Featuring a Digital Compute-in-Memory- Based DNN Accelerator Using an Ultra-Low-Power 13T-SRAM Cell. IEEE J. Solid State Circuits Haochen Zhang, Wei-Han Yu, Zhizhan Yang, Ka-Fai Un, Jun Yin, Rui Paulo Martins, Pui-In Mak
2025	—	`conf`	A 94.8nW Battery-Free Intelligent Silicon Platform Enabling Distributed, Adaptive, and Event-Driven Multimodal Sensing at the Edge. ISSCC Haochen Zhang, Wei-Han Yu, Zhongyu Zhao, Zhizhan Yang, Ka-Fai Un, Jun Yin, Rui Paulo Martins, Pui-In Mak
2025	J	`jnl`	A Cryo-CMOS Wideband Mode-Switching Class-F VCO With Harmonic-Resonance Self-Alignment. IEEE J. Solid State Circuits Yue Wu, Yatao Peng, Andrea Ruffino, Jad Benserhir, Jun Yin, Rui Paulo Martins, Pui-In Mak, Edoardo Charbon
2025	C	`conf`	A High Bandwidth Capacitorless NMOS LDO with Pole-Tracking Scheme and Adaptive FFRC Achieving -65dB PSR across Full Load Range. ISCAS Jinshuo Xu, Xiaoyan Zhao, Xiangyu Mao, Jun Yin, Mo Huang, Yan Lu
2025	J	`jnl`	A Series-LC-Assisted Oscillator Achieving -140.2 dBc/Hz Phase Noise and 187.5 dBc/Hz FoM at 10 MHz Offset From 10.7 GHz. IEEE Trans. Circuits Syst. II Express Briefs Xiangxun Zhan, Jun Yin, Rui Paulo Martins, Pui-In Mak
2025	J	`jnl`	A Systematic Review of Voltage Reference Circuits: Spanning Room Temperature to Cryogenic Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Chen Deng, Sai Wu, Chengcheng Liu, Yatao Peng, Man-Kay Law, Jun Yin, Rui Paulo Martins, Pui-In Mak
2025	J	`jnl`	An 840-to-970 MHz Multimodal Wake-Up Receiver With a Q-Equalized Antenna-ED Interface and 2-Dimensional Wake-Up Identification. IEEE Trans. Circuits Syst. I Regul. Pap. Zhizhan Yang, Haochen Zhang, Jun Yin, Rui Paulo Martins, Pui-In Mak
2025	J	`jnl`	Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL. IEEE Trans. Circuits Syst. I Regul. Pap. Jingrun Song, Xinyu Yang, Jiaxu Liu, Yueduo Liu, Zihao Zhu, Zhengxuan Han, Zehao Zhang, Jiaxin Liu, Hongshuai Zhang, Jun Yin, Pui-In Mak, Shiheng Yang
2025	J	`jnl`	Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction. IEEE Trans. Circuits Syst. II Express Briefs Tailong Xu, Haoran Li, Xi Meng, Xiangxun Zhan, Yatao Peng, Jun Yin, Shiheng Yang, Chao Fan, Zhixiang Huang, Rui Paulo Martins, Pui-In Mak
2025	J	`jnl`	Design and Analysis of a Type-II Sampling PLL With Automatic Frequency and Phase Calibrations Achieving 0.62-μs Locking Time. IEEE Trans. Circuits Syst. I Regul. Pap. Jian Yang, Tailong Xu, Xi Meng, Zhenghao Li, Jun Yin, Rui Paulo Martins, Pui-In Mak, Quan Pan
2024	—	`conf`	10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment. ISSCC Haoran Li, Tailong Xu, Xi Meng, Jun Yin, Rui Paulo Martins, Pui-In Mak
2024	—	`conf`	19.4 A 0.07 mm ISSCC Ya Zhao, Chao Fan, Qiuyu Fang, Guohe Zhang, Jun Yin, Pui-In Mak, Li Geng
2024	J	`jnl`	A 12.9-to-24 GHz Dual-Mode Multi-Coil VCO Achieving 199.2 dBc/Hz Peak FoM IEEE Trans. Circuits Syst. II Express Briefs Ya Zhao, Chao Fan, Yuanxing Peng, Chenglong Liang, Jun Yin, Pui-In Mak, Li Geng
2024	J	`jnl`	A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment. IEEE J. Solid State Circuits Haoran Li, Tailong Xu, Xi Meng, Jun Yin, Rui Paulo Martins, Pui-In Mak
2024	J	`jnl`	A 5.6-dB Noise Figure, 63-86-GHz Receiver Using a Wideband Noise-Cancelling Low Noise Amplifier With Phase and Amplitude Compensation. IEEE Trans. Circuits Syst. I Regul. Pap. Changxuan Han, Zhixian Deng, Yiyang Shu, Jun Yin, Pui-In Mak, Xun Luo
2024	—	`conf`	A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS. CICC Jian Yang, Tailong Xu, Xi Meng, Zhenghao Li, Jun Yin, Pui-In Mak, Rui Paulo Martins, Quan Pan
2024	J	`jnl`	A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Yueduo Liu, Zihao Zhu, Rongxin Bao, Jiahui Lin, Jun Yin, Qiang Li, Pui-In Mak, Shiheng Yang
2024	J	`jnl`	A Complementary Drain-Grounded VCO-PA Improving Transmit Efficiency Over a Wide EIRP Range. IEEE Trans. Circuits Syst. II Express Briefs Zhizhan Yang, Jun Yin, Rui Paulo Martins, Pui-In Mak
2024	J	`jnl`	A Radio-Frequency Cross-Connected Rectifier With LC Source Degeneration. IEEE Trans. Circuits Syst. I Regul. Pap. Qiujin Chen, Mo Huang, Tian Xia, Jun Yin, Haiwen Liu, Rui Paulo Martins, Yan Lu
2024	J	`jnl`	A ULP Long-Range Active-RF Tag With Automatically Calibrated Antenna-TRX Interface. IEEE J. Solid State Circuits Zhizhan Yang, Jun Yin, Wei-Han Yu, Haochen Zhang, Rui Paulo Martins, Pui-In Mak
2024	—	`conf`	A Wide-Load-Range High-PSR Capless Low-Dropout Regulator with Adaptive Supply-Ripple Cancellation. ICTA Linzhi Xie, Xiangyu Mao, Jun Yin, Yan Lu
2024	—	`conf`	An FVF-LDO with Differential EA and Push-Pull Super Source Follower for Fast Transient Response. ICTA Ruiyuan Chen, Xiangyu Mao, Jun Yin, Yan Lu
2024	J	`jnl`	Analysis and Design of a 21.2-to-25.5-GHz Triple-Coil Transformer-Coupled QVCO. IEEE Trans. Circuits Syst. I Regul. Pap. Ya Zhao, Chao Fan, Jun Yin, Pui-In Mak, Li Geng
2023	J	`jnl`	A 0.0043-mm IEEE Trans. Very Large Scale Integr. Syst. Yuchen Wei, Shiheng Yang, Yueduo Liu, Rongxin Bao, Zihao Zhu, Jiahui Lin, Zehao Zhang, Yong Chen, Jun Yin, Pui-In Mak, Qiang Li
2023	—	`conf`	A 13.5-to-28.8GHz 72.3%-Locking Range Multi-Phase Injection-Locked Frequency Tripler with Improved Output Power and Wideband Subharmonic-Spur Rejection in 28nm CMOS. CICC Chao Fan, Ya Zhao, Yanlong Zhang, Jun Yin, Pui-In Mak, Guohe Zhang, Li Geng
2023	—	`conf`	A 22.4-to-26.8GHz Dual-Path-Synchronized Quad-Core Oscillator Achieving -138dBc/Hz PN and 193.3dBc/Hz FoM at 10MHz Offset from 25.8GHz. ISSCC Xiangxun Zhan, Jun Yin, Pui-In Mak, Rui Paulo Martins
2023	J	`jnl`	A 3.57-mW 2.88-GHz Multi-Phase Injection-Locked Ring-VCO With a 200-kHz 1/f³ Phase Noise Corner. IEEE Trans. Circuits Syst. II Express Briefs Chao Fan, Ya Zhao, Yanlong Zhang, Jun Yin, Li Geng, Pui-In Mak
2023	—	`conf`	A ULP Long-Range Active-RF Tag with Automatic Antenna-Interface Calibration Achieving 20.5% TX Efficiency at -22dBm EIRP, and -60.4dBm Sensitivity at 17.8nW RX Power. ISSCC Zhizhan Yang, Jun Yin, Wei-Han Yu, Haochen Zhang, Pui-In Mak, Rui Paulo Martins
2023	J	`jnl`	Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion. IEEE Trans. Circuits Syst. I Regul. Pap. Xi Meng, Haoran Li, Peng Chen, Jun Yin, Pui-In Mak, Rui Paulo Martins
2023	J	`jnl`	On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up. IEEE Trans. Circuits Syst. II Express Briefs Zehao Zhang, Shiheng Yang, Yueduo Liu, Zihao Zhu, Jiahui Lin, Rongxin Bao, Tailong Xu, Zhizhan Yang, Mingkang Zhang, Jiaxin Liu, Xiong Zhou, Jun Yin, Pui-In Mak, Qiang Li
2022	J	`jnl`	A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Peng Chen, Xi Meng, Jun Yin, Pui-In Mak, Rui Paulo Martins, Robert Bogdan Staszewski
2022	J	`jnl`	A 6-to-7.5-GHz 54-fs IEEE Trans. Circuits Syst. I Regul. Pap. Tailong Xu, Shenke Zhong, Jun Yin, Pui-In Mak, Rui Paulo Martins
2022	J	`jnl`	Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop. IEEE Trans. Circuits Syst. I Regul. Pap. Yueduo Liu, Rongxin Bao, Zihao Zhu, Shiheng Yang, Xiong Zhou, Jun Yin, Pui-In Mak, Qiang Li
2022	J	`jnl`	Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Peng Chen, Jun Yin, Feifei Zhang, Pui-In Mak, Rui Paulo Martins, Robert Bogdan Staszewski
2021	—	`conf`	A 15.2-to-18.2GHz Balanced Dual-Core Inverse-Class-F VCO with Q-Enhanced 2 A-SSCC Xi Meng, Junqi Guo, Haoran Li, Jun Yin, Pui-In Mak, Rui Paulo Martins
2021	J	`jnl`	A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Shiheng Yang, Jun Yin, Tailong Xu, Taimo Yi, Pui-In Mak, Qiang Li, Rui Paulo Martins
2021	—	`conf`	A Periodically Time-Varying Inductor Applied to The Class-D VCO for Phase Noise Improvement. ESSCIRC Jun Yin, Pui-In Mak, Rui Paulo Martins
2021	J	`jnl`	A Wide-PCE-Dynamic-Range CMOS Cross-Coupled Differential-Drive Rectifier for Ambient RF Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs Gabriel Chong, Harikrishnan Ramiah, Jun Yin, Jagadheswaran Rajendran, Pui-In Mak, Rui Paulo Martins
2021	J	`jnl`	An 800 MHz-to-3.3 GHz 20-MHz Channel Bandwidth WPD CMOS Power Amplifier For Multiband Uplink Radio Transceivers. IEEE Trans. Circuits Syst. II Express Briefs Selvakumar Mariappan, Jagadheswaran Rajendran, Harikrishnan Ramiah, Pui-In Mak, Jun Yin, Rui Paulo Martins
2021	J	`jnl`	Bird's-eye view of analog and mixed-signal chips for the 21st century. Int. J. Circuit Theory Appl. Rui Paulo Martins, Pui-In Mak, Chi-Hang Chan, Jun Yin, Yan Zhu, Yong Chen, Yan Lu, Man-Kay Law, Sai-Weng Sin
2020	—	`conf`	10.1 A 1.4-to-2.7GHz FDD SAW-Less Transmitter for 5G-NR Using a BW-Extended N-Path Filter-Modulator, an Isolated-BB Input and a Wideband TIA-Based PA Driver Achieving <-157.5dBc/Hz OB Noise. ISSCC Gengzhen Qi, Haijun Shao, Pui-In Mak, Jun Yin, Rui Paulo Martins
2020	—	`conf`	17.9 A 9mW 54.9-to-63.5GHz Current-Reuse LO Generator with a 186.7dBc/Hz FoM by Unifying a 20GHz 3 ISSCC Chao Fan, Jun Yin, Chee-Cheow Lim, Pui-In Mak, Rui Paulo Martins
2020	J	`jnl`	A 1-V 4-mW Differential-Folded Mixer With Common-Gate Transconductor Using Multiple Feedback Achieving 18.4-dB Conversion Gain, +12.5-dBm IIP3, and 8.5-dB NF. IEEE Trans. Very Large Scale Integr. Syst. Nandini Vitee, Harikrishnan Ramiah, Pui-In Mak, Jun Yin, Rui Paulo Martins
2020	J	`jnl`	A 3.15-mW +16.0-dBm IIP3 22-dB CG Inductively Source Degenerated Balun-LNA Mixer With Integrated Transformer-Based Gate Inductor and IM2 Injection Technique. IEEE Trans. Very Large Scale Integr. Syst. Nandini Vitee, Harikrishnan Ramiah, Pui-In Mak, Jun Yin, Rui Paulo Martins
2020	J	`jnl`	A Multiband FDD SAW-Less Transmitter for 5G-NR Featuring a BW-Extended N-Path Filter-Modulator, a Switched-BB Input, and a Wideband TIA-Based PA Driver. IEEE J. Solid State Circuits Gengzhen Qi, Haijun Shao, Pui-In Mak, Jun Yin, Rui Paulo Martins
2020	J	`jnl`	A Single-Pin Antenna Interface RF Front End Using a Single-MOS DCO-PA and a Push-Pull LNA. IEEE J. Solid State Circuits Kai Xu, Jun Yin, Pui-In Mak, Robert Bogdan Staszewski, Rui Paulo Martins
2020	J	`jnl`	Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools. IEEE Trans. Circuits Syst. Ricardo Martins, Nuno Lourenço, Nuno Horta, Shenke Zhong, Jun Yin, Pui-In Mak, Rui Paulo Martins
2019	J	`jnl`	A 0.0056-mm IEEE J. Solid State Circuits Shiheng Yang, Jun Yin, Pui-In Mak, Rui Paulo Martins
2019	J	`jnl`	A 0.12-mm IEEE Trans. Circuits Syst. I Regul. Pap. Ka-Fai Un, Gengzhen Qi, Jun Yin, Shiheng Yang, Shupeng Yu, Chio-In Ieong, Pui-In Mak, Rui Paulo Martins
2019	J	`jnl`	A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS. IEEE J. Solid State Circuits Shiheng Yang, Jun Yin, Haidong Yi, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2019	J	`jnl`	A 0.5-V 0.4-to-1.6-GHz 8-Phase Bootstrap Ring-VCO Using Inherent Non-Overlapping Clocks Achieving a 162.2-dBc/Hz FoM. IEEE Trans. Circuits Syst. II Express Briefs Tongquan Jiang, Jun Yin, Pui-In Mak, Rui Paulo Martins
2019	J	`jnl`	A 5.1-to-7.3 mW, 2.4-to-5 GHz Class-C Mode-Switching Single-Ended-Complementary VCO Achieving >190 dBc/Hz FoM. IEEE Trans. Circuits Syst. II Express Briefs Chee-Cheow Lim, Harikrishnan Ramiah, Jun Yin, Narendra Kumar, Pui-In Mak, Rui Paulo Martins
2019	J	`jnl`	A Comparative Study of 8-Phase Feedforward-Coupling Ring VCOs. IEEE Trans. Circuits Syst. II Express Briefs Iat-Fai Sun, Jun Yin, Pui-In Mak, Rui Paulo Martins
2019	J	`jnl`	A coin-battery-powered LDO-Free 2.4-GHz Bluetooth Low Energy/ZigBee receiver consuming 2 mA. Integr. Zechariah Balan, Harikrishnan Ramiah, Jagadheswaran Rajendran, Nandini Vitee, Pravinah Nair Shasidharan, Jun Yin, Pui-In Mak, Rui Paulo Martins
2019	J	`jnl`	CMOS Cross-Coupled Differential-Drive Rectifier in Subthreshold Operation for Ambient RF Energy Harvesting - Model and Analysis. IEEE Trans. Circuits Syst. II Express Briefs Gabriel Chong, Harikrishnan Ramiah, Jun Yin, Jagadheswaran Rajendran, Wei Ru Wong, Pui-In Mak, Rui Paulo Martins
2019	—	`conf`	Magnetic-Tuning Millimeter-Wave CMOS Oscillators (Invited Paper). CICC Xiaolong Liu, Zhiqiang Huang, Jun Yin, Howard C. Luong
2019	J	`jnl`	Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications. IEEE Trans. Very Large Scale Integr. Syst. Ricardo Martins, Nuno Lourenço, Nuno Horta, Jun Yin, Pui-In Mak, Rui Paulo Martins
2019	—	`conf`	Using EDA Tools to Push the Performance Boundaries of an Ultralow-Power IoT-VCO at 65nm. SMACD Ricardo Martins, Nuno Lourenço, Nuno Horta, Jun Yin, Pui-In Mak, Rui Paulo Martins
2018	—	`conf`	A 0.0056mm ISSCC Shiheng Yang, Jun Yin, Pui-In Mak, Rui Paulo Martins
2018	J	`jnl`	A 0.032-mm IEEE Trans. Circuits Syst. II Express Briefs Haidong Yi, Jun Yin, Pui-In Mak, Rui Paulo Martins
2018	J	`jnl`	A 0.18-V 382-µW Bluetooth Low-Energy Receiver Front-End With 1.33-nW Sleep Power for Energy-Harvesting Applications in 28-nm CMOS. IEEE J. Solid State Circuits Haidong Yi, Wei-Han Yu, Pui-In Mak, Jun Yin, Rui Paulo Martins
2018	—	`conf`	A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS. ISSCC Jun Yin, Shiheng Yang, Haidong Yi, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2018	—	`conf`	A 2.4-GHz Single-Pin Antenna Interface RF Front-End with a Function-Reuse Single-MOS VCO-PA and a Push-Pull LNA. A-SSCC Kai Xu, Jun Yin, Pui-In Mak, Robert Bogdan Staszewski, Rui Paulo Martins
2018	J	`jnl`	A Coin-Battery-Powered LDO-Free 2.4-GHz Bluetooth Low-Energy Transmitter With 34.7% Peak System Efficiency. IEEE Trans. Circuits Syst. II Express Briefs Xingqiang Peng, Jun Yin, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2018	J	`jnl`	An Inverse-Class-F CMOS Oscillator With Intrinsic-High-Q First Harmonic and Second Harmonic Resonances. IEEE J. Solid State Circuits Chee-Cheow Lim, Harikrishnan Ramiah, Jun Yin, Pui-In Mak, Rui Paulo Martins
2018	—	`conf`	An inverse-class-F CMOS VCO with intrinsic-high-Q 1 ISSCC Chee-Cheow Lim, Jun Yin, Pui-In Mak, Harikrishnan Ramiah, Rui Paulo Martins
2018	—	`conf`	Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications. SMACD Ricardo Martins, Nuno Lourenço, Nuno Horta, Jun Yin, Pui-In Mak, Rui Paulo Martins
2018	J	`jnl`	Low-Phase-Noise Wideband Mode-Switching Quad-Core-Coupled mm-wave VCO Using a Single-Center-Tapped Switched Inductor. IEEE J. Solid State Circuits Yatao Peng, Jun Yin, Pui-In Mak, Rui Paulo Martins
2017	—	`conf`	24.4 A 0.18V 382µW bluetooth low-energy (BLE) receiver with 1.33nW sleep power for energy-harvesting applications in 28nm CMOS. ISSCC Wei-Han Yu, Haidong Yi, Pui-In Mak, Jun Yin, Rui Paulo Martins
2017	J	`jnl`	A 2.4-GHz ZigBee Transmitter Using a Function-Reuse Class-F DCO-PA and an ADPLL Achieving 22.6% (14.5%) System Efficiency at 6-dBm (0-dBm) P IEEE J. Solid State Circuits Xingqiang Peng, Jun Yin, Pui-In Mak, Wei-Han Yu, Rui Paulo Martins
2016	—	`conf`	2.7 A 0.003mm2 1.7-to-3.5GHz dual-mode time-interleaved ring-VCO achieving 90-to-150kHz 1/f3 phase-noise corner. ISSCC Jun Yin, Pui-In Mak, Franco Maloberti, Rui Paulo Martins
2016	J	`jnl`	A 0.05- to 10-GHz, 19- to 22-GHz, and 38- to 44-GHz Frequency Synthesizer for Software-Defined Radios in 0.13-µm CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs Sujiang Rong, Jun Yin, Howard C. Luong
2016	J	`jnl`	A Time-Interleaved Ring-VCO with Reduced 1/f IEEE J. Solid State Circuits Jun Yin, Pui-In Mak, Franco Maloberti, Rui Paulo Martins
2016	C	`conf`	A high-Q spiral inductor with dual-layer patterned floating shield in a class-B VCO achieving a 190.5-dBc/Hz FoM. ISCAS Chee-Cheow Lim, Harikrishnan Ramiah, Jun Yin, Pui-In Mak, Rui Paulo Martins
2014	—	`conf`	A 0.37-to-46.5GHz frequency synthesizer for software-defined radios in 65nm CMOS. VLSIC Jun Yin, Howard C. Luong
2014	J	`jnl`	A 21-48 GHz Subharmonic Injection-Locked Fractional-N Frequency Synthesizer for Multiband Point-to-Point Backhaul Communications. IEEE J. Solid State Circuits Alvin Li, Shiyuan Zheng, Jun Yin, Xun Luo, Howard C. Luong
2013	J	`jnl`	A 57.5-90.1-GHz Magnetically Tuned Multimode CMOS VCO. IEEE J. Solid State Circuits Jun Yin, Howard C. Luong
2013	—	`conf`	A CMOS 21-48GHz fractional-N synthesizer employing ultra-wideband injection-locked frequency multipliers. CICC Alvin Li, Shiyuan Zheng, Jun Yin, Howard C. Luong, Xun Luo
2012	—	`conf`	A 57.5-to-90.1GHz magnetically-tuned multi-mode CMOS VCO. CICC Jun Yin, Howard C. Luong
2010	J	`jnl`	A System-on-Chip EPC Gen-2 Passive UHF RFID Tag With Embedded Temperature Sensor. IEEE J. Solid State Circuits Jun Yin, Jun Yi, Matthew K. Law, Yunxiao Ling, Man Chiu Lee, Kwok Ping Ng, Bo Gao, Howard C. Luong, Amine Bermak, Mansun Chan, Wing-Hung Ki, Chi-Ying Tsui, Matthew M. F. Yuen
2010	—	`conf`	A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor. ISSCC Jun Yin, Jun Yi, Man Kay Law, Yunxiao Ling, Man Chiu Lee, Kwok Ping Ng, Bo Gao, Howard C. Luong, Amine Bermak, Mansun Chan, Wing-Hung Ki, Chi-Ying Tsui, Matthew Ming-Fai Yuen