Jun Yang - RankMe

202 papers A* 9A 7B 2C 5Journal 119Unranked 59

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	30.1 A 28nm 127.54TFLOPS/W MXFP6 and 117.42TFLOPS/W MXFP8 Compute-in-Memory Macro with Adaptive-Preserved-Bit-Width and Serial-Dual-Bit-Sliding Schemes. ISSCC Xing Wang, Yucheng Du, Tianhui Jiao, Defa Wu, Xi Chen, Miaoyu Tang, Yi Yang, Zhichao Liu, An Guo, Gaoming Fu, Peng Li, Jun Dong, Bo Liu, Xinning Liu, Weiwei Shan, Hao Cai, Guangyu Sun, Lin Tong, Jun Yang, Xin Si
2026	—	`conf`	A 51.6μJ/Token Subspace-Rotation-Based Dual-Quantized Large-language-Model Accelerator with Fused Scale-Activation INT Datapath and Rearranged Bit-Slice LUT Computation. ISSCC Bo Liu, Zihan Zou, Xinming Yan, Xilong Kang, Xinyang Chen, Bo Hu, Jiaming Lin, Haoran Du, Jun Yang, Xin Si, Hao Cai
2026	J	`jnl`	CIM-Tuner: Balancing the Compute and Storage Capacity of SRAM-CIM Accelerator via Hardware-mapping Co-exploration. CoRR Jinwu Chen, Yuhui Shi, He Wang, Zhe Jiang, Jun Yang, Xin Si, Zhenhua Zhu
2026	A*	`conf`	ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications. AAAI Changwen Xing, SamZaak Wong, Xinlai Wan, Yanfeng Lu, Mengli Zhang, Zebin Ma, Lei Qi, Zhengxiong Li, Nan Guan, Zhe Jiang, Xi Wang, Jun Yang
2026	J	`jnl`	EMO-CIM: An Input/Stationary-Data Similarity-Aware Computing-In-Memory Design for Variable Vector-Wise Computation in Edge Multioperator AI Acceleration. IEEE Solid State Circuits Lett. Bo Wang, Yuchen Tang, Feiran Liu, Xiaoxue Zhong, Yuchen Ma, Xin Si, Jun Yang
2026	A*	`conf`	FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification. AAAI Gwok-Waa Wan, SamZaak Wong, Shengchu Su, Chenxu Niu, Ning Wang, Xinlai Wan, Qixiang Chen, Mengnv Xing, Jingyi Zhang, Jianmin Ye, Yubo Wang, Rongchang Song, Tao Ni, Qiang Xu, Nan Guan, Zhe Jiang, Xi Wang, Yong Chen, Jun Yang
2026	J	`jnl`	RTLocating: Intent-aware RTL Localization for Hardware Design Iteration. CoRR Changwen Xing, Yanfeng Lu, Lei Qi, Chenxu Niu, Jie Li, Xi Wang, Yong Chen, Jun Yang
2026	J	`jnl`	StatCHAR: Statistical Timing Characterization Framework via Heterogeneous Graph Attention Network and Active Learning With Parasitic RC Reduction. IEEE Trans. Circuits Syst. I Regul. Pap. Peng Cao, Zeyuan Deng, Yuhan Dong, Xu Cheng, Yuyang Ye, Jun Yang
2026	J	`jnl`	VRM: Teaching Reward Models to Understand Authentic Human Preferences. CoRR Biao Liu, Ning Xu, Jun Yang, Hao Xu, Xin Geng
2025	—	`conf`	14.3 A 28nm 17.83-to-62.84TFLOPS/W Broadcast-Alignment Floating-Point CIM Macro with Non-Two's-Complement MAC for CNNs and Transformers. ISSCC Xing Wang, Tianhui Jiao, Yi Yang, Shaochen Li, Dongqi Li, An Guo, Yuhui Shi, Yuchen Tang, Jinwu Chen, Zhican Zhang, Zhichao Liu, Bo Liu, Weiwei Shan, Xin Wang, Hao Cai, Wenwu Zhu, Jun Yang, Xin Si
2025	—	`conf`	14.6 A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer. ISSCC Xi Chen, Shaochen Li, Zhican Zhang, Wentao Zheng, Xiao Tan, Yuchen Tang, Yuhui Shi, Lizheng Ren, Yibo Mai, Feiran Liu, Jinwu Chen, Zhaoyang Zhang, An Guo, Tianzhu Xiong, Bo Wang, Xinning Liu, Weiwei Shan, Bo Liu, Hao Cai, Jun Yang, Xin Si
2025	—	`conf`	14.7 NeuroPilot: A 28nm, 69.4fJ/node and 0.22ns/node, 32×32 Mimetic-Path-Searching CIM-Macro with Dynamic-Logic Pilot PE and Dual-Direction Searching. ISSCC An Guo, Jingmin Zhang, Xingyu Pu, Yi Yang, Defa Wu, Yuchen Tang, Yuhui Shi, Yinghai Gao, Zhichao Liu, Bo Wang, Tianzhu Xiong, Zhaoyang Zhang, Xi Chen, Jinwu Chen, Feiran Liu, Xing Wang, Xinning Liu, Weiwei Shan, Bo Liu, Hao Cai, Xin Si, Jun Yang
2025	J	`jnl`	A 22-nm 64-kB lightning-like hybrid computing-in-memory macro with a compressed adder tree and analog-storage quantizers for transformer and CNNs. Sci. China Inf. Sci. An Guo, Xi Chen, Fangyuan Dong, Jinwu Chen, Zhihang Yuan, Xing Hu, Guangyu Sun, Xiaomin Li, Arindam Basu, Jun Yang, Xin Si
2025	J	`jnl`	A 28 nm 128-kb Exponent- and Mantissa-Computation-In-Memory Dual-Macro for Floating-Point and INT CNNs. IEEE J. Solid State Circuits An Guo, Xueshan Dong, Fangyuan Dong, Dongqi Li, Yiran Zhang, Jingmin Zhang, Jun Yang, Xin Si
2025	J	`jnl`	A 28-nm 16-kb Aggregation and Combination Computing-in-Memory Macro With Dual-Level Sparsity Modulation and Sparse-Tracking ADCs for GCNs. IEEE J. Solid State Circuits Zhaoyang Zhang, Yanqi Zhang, Feiran Liu, Zhichao Liu, Yinhai Gao, Yuchen Ma, Yutong Zhang, An Guo, Tianzhu Xiong, Jinwu Chen, Xi Chen, Bo Wang, Yuchen Tang, Jun Yang, Xin Si
2025	—	`conf`	A 40nm 4Mb High-Reliability STT-MRAM Achieving 18ns Write-Time and 94.9% Wafer-Level-Die-Yield Across -55°C-to-125°C. CICC Yaoru Hou, Haoran Du, Jiongzhe Su, Yibo Liu, Zhenghan Fang, Jia-Le Cui, Shuyu Wang, Chenxing Liu-Sun, Xuezhao Wu, Zhihua Xiao, Bo Liu, Xin Si, Jun Yang, Qiming Shao, Hao Cai
2025	—	`conf`	A 52.03TOPS/W DCIM-Based Accelerator with FlashAttention and Sparsity-Aware Alignment for LLMs. CICC Bo Liu, Xingyu Xu, Yang Zhang, Xilong Kang, Qingwen Wei, Zihan Zou, Jun Yang, Hao Cai, Xin Si
2025	J	`jnl`	A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation. IEEE Trans. Very Large Scale Integr. Syst. Tianzhu Xiong, Yuyang Ye, Xin Si, Jun Yang
2025	J	`jnl`	A Path Statistical Delay Prediction Framework Based on Global Graph Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. Jingjing Guo, Xuejie Ning, Chenfei Hua, Jun Yang, Zhikuang Cai
2025	J	`jnl`	A Proactive Droop Mitigation Technique Using Dual-Proportional-Derivative Controller Based on Current and Voltage Prediction. IEEE J. Solid State Circuits Kaize Zhou, Weiwei Shan, Keran Li, Zhuo Chen, Haitao Ge, Jun Yang
2025	J	`jnl`	ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications. CoRR Changwen Xing, SamZaak Wong, Xinlai Wan, Yanfeng Lu, Mengli Zhang, Zebin Ma, Lei Qi, Zhengxiong Li, Nan Guan, Zhe Jiang, Xi Wang, Jun Yang
2025	A	`conf`	DiSPlace: Diffusion-Sharing-Driven Transistor-Level Placement Beyond Standard-Cell Boundaries for DTCO. ICCAD Keyu Peng, Yinuo Wu, Zhengzhe Zheng, Hao Gu, Ziran Zhu, Chao Wang, Jun Yang
2025	J	`jnl`	Dual Multimodal Fusions With Convolution and Transformer Layers for VLSI Congestion Prediction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hao Gu, Youwen Wang, Xinglin Zheng, Keyu Peng, Ziran Zhu, Jianli Chen, Jun Yang
2025	—	`conf`	EDA-Debugger: An LLM-Based Framework for Automated EDA Runtime Issue Resolution. ISQED Junyan Li, Sam-Zaak Wong, Gwok-Waa Wan, Xi Wang, Jun Yang
2025	J	`jnl`	Expansion of the memory pyramid in the era of large models: compute-intensive compute-in-memory and memory-intensive compute-in-memory. Sci. China Inf. Sci. Zhichao Liu, Yanqi Zhang, Zhican Zhang, Yi Yang, Zhaoyang Zhang, Xing Wang, Jinwu Chen, Xiaomin Li, Xin Si, Jun Yang
2025	J	`jnl`	ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA. CoRR Zhengyuan Shi, Zeju Li, Chengyu Ma, Yunhao Zhou, Ziyang Zheng, Jiawei Liu, Hongyang Pan, Lingfeng Zhou, Kezhi Li, Jiaying Zhu, Lingwei Yan, Zhiqiang He, Chenhao Xue, Wentao Jiang, Fan Yang, Guangyu Sun, Xiaoyan Yang, Gang Chen, Chuan Shi, Zhufei Chu, Jun Yang, Qiang Xu
2025	—	`conf`	GCNIM: A Booth-6T-SRAM Based Graph-Convolutional-Networks-in-Memory Computing Macro. MCSoC Yan Yan, Zhaoyang Zhang, Shaochen Li, Defa Wu, Jun Yang, Xin Si
2025	J	`jnl`	Image2Net: Datasets, Benchmark and Hybrid Framework to Convert Analog Circuit Diagrams into Netlists. CoRR Haohang Xu, Chengjie Liu, Qihang Wang, Wenhao Huang, Yongjian Xu, Weiyu Chen, Anlan Peng, Zhijun Li, Bo Li, Lei Qi, Jun Yang, Yuan Du, Li Du
2025	A*	`conf`	LAD: Efficient Accelerator for Generative Inference of LLM with Locality Aware Decoding. HPCA Haoran Wang, Yuming Li, Haobo Xu, Ying Wang, Liqi Liu, Jun Yang, Yinhe Han
2025	A	`conf`	MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs. ICCAD Chenchen Zhao, Zhengyuan Shi, Xiangyu Wen, Chengjie Liu, Yi Liu, Yunhao Zhou, Yuxiang Zhao, Hefei Feng, Yinan Zhu, Gwok-Waa Wan, Xin Cheng, Weiyu Chen, Yongqi Fu, Chujie Chen, Chenhao Xue, Ying Wang, Yibo Lin, Jun Yang, Ning Xu, Xi Wang, Qiang Xu
2025	J	`jnl`	MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs. CoRR Chenchen Zhao, Zhengyuan Shi, Xiangyu Wen, Chengjie Liu, Yi Liu, Yunhao Zhou, Yuxiang Zhao, Hefei Feng, Yinan Zhu, Gwok-Waa Wan, Xin Cheng, Weiyu Chen, Yongqi Fu, Chujie Chen, Chenhao Xue, Guangyu Sun, Ying Wang, Yibo Lin, Jun Yang, Ning Xu, Xi Wang, Qiang Xu
2025	—	`conf`	Post-Routing Path Statistical Delay Estimation Based on SGAT-GRU Prediction Framework. MLCAD Jingjing Guo, Xuejie Ning, Suohang Yang, Jun Yang, Zhikuang Cai
2025	J	`jnl`	Preference Orchestrator: Prompt-Aware Multi-Objective Alignment for Large Language Models. CoRR Biao Liu, Ning Xu, Jun Yang, Xin Geng
2025	J	`jnl`	Routability-Driven Macro Placement Engine for Modern FPGAs With Complex Cascade Shape and Region Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hao Gu, Jian Gu, Keyu Peng, Jianli Chen, Jun Yang, Ziran Zhu
2025	A*	`conf`	Truly Pre-Routing Timing Prediction via Considering Power Delivery Network. DAC Yuyang Ye, Mingwei He, Lizheng Ren, Jianwang Zhai, Tinghuan Chen, Jun Yang, Longxing Shi
2025	J	`jnl`	VCD-CIM: A Vertical-Compute-Decode Digital Computing-In-Memory Area-Efficient Macro for Vector-Wise Computation With Variable Accumulation Length. IEEE Access Bo Wang, Xiaoxue Zhong, Jun Yang
2025	J	`jnl`	cuPilot: A Strategy-Coordinated Multi-agent Framework for CUDA Kernel Evolution. CoRR Jinwu Chen, Qidie Wu, Bin Li, Lin Ma, Xin Si, Yang Hu, Shouyi Yin, Jun Yang
2024	—	`conf`	14.2 Proactive Voltage Droop Mitigation Using Dual-Proportional-Derivative Control Based on Current and Voltage Prediction Applied to a Multicore Processor in 28nm CMOS. ISSCC Weiwei Shan, Kaize Zhou, Keran Li, Yuxuan Du, Zhuo Chen, Junyi Qian, Haitao Ge, Jun Yang, Xin Si
2024	—	`conf`	22 nm Ultra-Low Power MCU with 43.5nW/KB Sleep Retention Power for Automotive Grade-1 Applications. ICTA Yibo Liu, Wen Wang, Hongjin Zhu, Longning Qi, Bo Liu, Xinning Liu, Jun Yang, Hao Cai
2024	—	`conf`	34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs. ISSCC An Guo, Xi Chen, Fangyuan Dong, Jinwu Chen, Zhihang Yuan, Xing Hu, Yuanpeng Zhang, Jingmin Zhang, Yuchen Tang, Zhican Zhang, Gang Chen, Dawei Yang, Zhaoyang Zhang, Lizheng Ren, Tianzhu Xiong, Bo Wang, Bo Liu, Weiwei Shan, Xinning Liu, Hao Cai, Guangyu Sun, Jun Yang, Xin Si
2024	J	`jnl`	A 0.65 V 4 dB NF 2.4 GHz Sub-Passive RF Down-Converter With Trans-Frequency Current-Reusing Scheme Achieving Low Flicker Noise and High Linearity. IEEE Trans. Circuits Syst. I Regul. Pap. Yan Zhao, Chao Chen, Jun Yang
2024	J	`jnl`	A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. IEEE J. Solid State Circuits An Guo, Chen Xi, Fangyuan Dong, Xingyu Pu, Dongqi Li, Jingmin Zhang, Xueshan Dong, Hui Gao, Yiran Zhang, Bo Wang, Jun Yang, Xin Si
2024	—	`conf`	A 28nm 128-kb Exponent- and Mantissa-Computation-InMemory Dual-macro for Floating-point and INT CNNs. A-SSCC An Guo, Xueshan Dong, Fangyuan Dong, Dongqi Li, Yiran Zhang, Jingmin Zhang, Yuchen Tang, Yuhui Shi, Xiao Tan, Bo Liu, Weiwei Shan, Hao Cai, Jun Yang, Xin Si
2024	—	`conf`	A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs. CICC Zhaoyang Zhang, Zhichao Liu, Feiran Liu, Yinhai Gao, Yuchen Ma, Yutong Zhang, An Guo, Tianzhu Xiong, Jinwu Chen, Xi Chen, Bo Wang, Yuchen Tang, Xingyu Pu, Xing Wang, Jun Yang, Xin Si
2024	J	`jnl`	A 55 μ W 2.4 GHz wake-up receiver with offset-based peak detection achieving -90dBm sensitivity for IoT applications. Microelectron. J. Yan Zhao, Chao Chen, Jun Yang
2024	J	`jnl`	A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip. IEEE J. Solid State Circuits Chuxiong Lin, Weifeng He, Yanan Sun, Lin Shao, Bo Zhang, Jun Yang, Mingoo Seok
2024	J	`jnl`	An Effective Routing Refinement Algorithm Based on Incremental Replacement and Rerouting. IEEE Trans. Circuits Syst. II Express Briefs Ziran Zhu, Fuheng Shen, Yangjie Mei, Jianli Chen, Jun Yang
2024	J	`jnl`	An analysis of TinyML@ICCAD for implementing AI on low-power microprocessor. Sci. China Inf. Sci. Guoqing Li, Jingwei Zhang, Meng Zhang, Tuo Li, Tinghuan Chen, Jun Yang
2024	J	`jnl`	CATCAM: a 28 nm constant-time alteration TCAM enabling less than 50 ns update latency. Sci. China Inf. Sci. Chenchen Deng, Tianzhu Xiong, Zhaoshi Li, Zhiwei Liu, Yao Wang, Jianfeng Zhu, Jun Yang, Shaojun Wei, Leibo Liu
2024	J	`jnl`	ChipExpert: The Open-Source Integrated-Circuit-Design-Specific Large Language Model. CoRR Ning Xu, Zhaoyang Zhang, Lei Qi, Wensuo Wang, Chao Zhang, Zihao Ren, Huaiyuan Zhang, Xin Cheng, Yanqi Zhang, Zhichao Liu, Qingwen Wei, Shiyang Wu, Lanlan Yang, Qianfeng Lu, Yiqun Ma, Mengyao Zhao, Junbo Liu, Yufan Song, Xin Geng, Jun Yang
2024	J	`jnl`	High-Performance 3-D Placement Engine With Physical-Aware Incremental Partitioning. IEEE Trans. Circuits Syst. II Express Briefs Ziran Zhu, Yuejian Shi, Yangjie Mei, Fuheng Shen, Hong Liu, Jun Yang
2024	J	`jnl`	High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ziran Zhu, Yangjie Mei, Kangkang Deng, Huan He, Jianli Chen, Jun Yang, Yao-Wen Chang
2024	J	`jnl`	Intrinsic MRAM Properties Enable Security Circuits. IEEE Trans. Circuits Syst. II Express Briefs Haoran Du, You Wang, Jun Yang, Hao Cai
2024	J	`jnl`	LAMPlace: Legalization-Aided Reinforcement Learning-Based Macro Placement for Mixed-Size Designs With Preplaced Blocks. IEEE Trans. Circuits Syst. II Express Briefs Hao Gu, Jian Gu, Keyu Peng, Ziran Zhu, Ning Xu, Xin Geng, Jun Yang
2024	A*	`conf`	Late Breaking Results: Routability-Driven FPGA Macro Placement Considering Complex Cascade Shape and Region Constraints. DAC Hao Gu, Jian Gu, Keyu Peng, Jun Yang, Ziran Zhu
2024	J	`jnl`	TICA: Timing Slack Inference and Clock Frequency Adaption Technique for a Deeply Pipelined Near-Threshold-Voltage Bitcoin Mining Core. IEEE J. Solid State Circuits Jieyu Li, Weifeng He, Bo Zhang, Guanghui He, Jing Jin, Jun Yang, Mingoo Seok
2024	B	`conf`	Variational Label-Correlation Enhancement for Congestion Prediction. ASPDAC Biao Liu, Congyu Qiao, Ning Xu, Xin Geng, Ziran Zhu, Jun Yang
2023	J	`jnl`	A 0.55V 10-Bit 100-MS/s SAR ADC With 3.6-fJ/Conversion-Step in 28nm CMOS for RF Receivers. IEEE Trans. Circuits Syst. II Express Briefs Yan Zhao, Chao Chen, Jun Yang
2023	—	`conf`	A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference. ISSCC Hao Cai, Zhongjian Bian, Yaoru Hou, Yongliang Zhou, Jia-Le Cui, Yanan Guo, Xiaoyun Tian, Bo Liu, Xin Si, Zhen Wang, Jun Yang, Weiwei Shan
2023	—	`conf`	A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. ISSCC An Guo, Xin Si, Xi Chen, Fangyuan Dong, Xingyu Pu, Dongqi Li, Yongliang Zhou, Lizheng Ren, Yeyang Xue, Xueshan Dong, Hui Gao, Yiran Zhang, Jingmin Zhang, Yuyao Kong, Tianzhu Xiong, Bo Wang, Hao Cai, Weiwei Shan, Jun Yang
2023	—	`conf`	A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks. ISSCC Bo Wang, Chen Xue, Zhongyuan Feng, Zhaoyang Zhang, Han Liu, Lizheng Ren, Xiang Li, Anran Yin, Tianzhu Xiong, Yeyang Xue, Shengnan He, Yuyao Kong, Yongliang Zhou, An Guo, Xin Si, Jun Yang
2023	J	`jnl`	AAD-KWS: A Sub-μ W Keyword Spotting Chip With an Acoustic Activity Detector Embedded in MFCC and a Tunable Detection Window in 28-nm CMOS. IEEE J. Solid State Circuits Weiwei Shan, Junyi Qian, Lixuan Zhu, Jun Yang, Cheng Huang, Hao Cai
2023	J	`jnl`	An Ultra-Low-Voltage 2.4-GHz Flicker-Noise-Free RF Receiver Front End Based on Switched-Capacitor Hybrid TIA With 4.5-dB NF and 11.5-dBm OIP3. IEEE J. Solid State Circuits Chao Chen, Dan Huang, Yan Zhao, Yuemin Jin, Jun Yang
2023	J	`jnl`	An efficient path delay variability model for wide-voltage-range digital circuits. Sci. China Inf. Sci. Weiwei Shan, Yuqiang Cui, Wentao Dai, Xinning Liu, Jingjing Guo, Peng Cao, Jun Yang
2023	J	`jnl`	Beyond Eliminating Timing Margin: An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator Without Accuracy Loss. IEEE J. Solid State Circuits Zhengguo Shen, Weiwei Shan, Yuxuan Du, Ziyu Li, Jun Yang
2023	J	`jnl`	Efficient and Accurate ECO Leakage Optimization Framework With GNN and Bidirectional LSTM. IEEE Trans. Very Large Scale Integr. Syst. Peng Cao, Guoqing He, Wenjie Ding, Zhanhua Zhang, Kai Wang, Jun Yang
2023	J	`jnl`	Evaluation Platform of Time-Domain Computing-in-Memory Circuits. IEEE Trans. Circuits Syst. II Express Briefs Yuyao Kong, Xi Chen, Xin Si, Jun Yang
2023	J	`jnl`	From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits. Sci. China Inf. Sci. Zhaoyang Zhang, Jinwu Chen, Xi Chen, An Guo, Bo Wang, Tianzhu Xiong, Yuyao Kong, Xingyu Pu, Shengnan He, Xin Si, Jun Yang
2023	J	`jnl`	Multi-sensor integrated navigation/positioning systems using data fusion: From analytics-based to learning-based approaches. Inf. Fusion Yuan Zhuang, Xiao Sun, You Li, Jianzhu Huai, Luchi Hua, Xiansheng Yang, Xiaoxiang Cao, Peng Zhang, Yue Cao, Longning Qi, Jun Yang, Nashwa El-Bendary, Naser El-Sheimy, John S. Thompson, Ruizhi Chen
2023	J	`jnl`	Multiplication Circuit Architecture for Error- Tolerant CNN-Based Keywords Speech Recognition. IEEE Des. Test Bo Liu, Hao Cai, Zilong Zhang, Xiaoling Ding, Renyuan Zhang, Yu Gong, Zhen Wang, Wei Ge, Jun Yang
2023	J	`jnl`	SmartFPS: Neural network based wireless-inertial fusion positioning system. Frontiers Neurorobotics Luchi Hua, Yuan Zhuang, Jun Yang
2023	J	`jnl`	Triplet MatchNet Based Indoor Position Method Using CSI Fingerprint Similarity Comparison. IEEE Trans. Veh. Technol. Hao Gu, Jun Yang, Guan Gui, Haris Gacanin
2023	J	`jnl`	Variational Label-Correlation Enhancement for Congestion Prediction. CoRR Biao Liu, Congyu Qiao, Ning Xu, Xin Geng, Ziran Zhu, Jun Yang
2022	—	`conf`	A 28nm, 4.69TOPS/W Training, 2.34µJ/lmage Inference, on-chip Training Accelerator with Inference-compatible Back Propagation. ICTA Haitao Ge, Weiwei Shan, Yicheng Lu, Jun Yang
2022	—	`conf`	A Quantization Model Based on a Floating-point Computing-in-Memory Architecture. APCCAS Xi Chen, An Guo, Xinbing Xu, Xin Si, Jun Yang
2022	A	`conf`	A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate Computing. DATE Bo Liu, Hao Cai, Xuan Zhang, Haige Wu, Anfeng Xue, Zilong Zhang, Zhen Wang, Jun Yang
2022	J	`jnl`	An Efficient BCNN Deployment Method Using Quality-Aware Approximate Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bo Liu, Ziyu Wang, Xuetao Wang, Renyuan Zhang, Anfeng Xue, Qiao Shen, Na Xie, Yu Gong, Zhen Wang, Jun Yang, Hao Cai
2022	—	`ch.`	Approximate Computing for Energy-Constrained DNN-Based Speech Recognition. Approximate Computing Bo Liu, Hao Cai, Zhen Wang, Jun Yang
2022	B	`conf`	Graph Convolutional Network Empowered Indoor Localization Method via Aggregating MIMO CSI. GLOBECOM Hao Gu, Jun Yang, Zhengran He, Guan Gui, Haris Gacanin
2022	A*	`conf`	High-performance placement for large-scale heterogeneous FPGAs with clock constraints. DAC Ziran Zhu, Yangjie Mei, Zijun Li, Jingwen Lin, Jianli Chen, Jun Yang, Yao-Wen Chang
2022	—	`conf`	MPAM: Reliable, Low-Latency, Near-Threshold-Voltage Multi-Voltage/Frequency-Domain Network-on-Chip with Metastability Risk Prediction and Mitigation. CICC Chuxiong Lin, Weifeng He, Yannan Sun, Lin Shao, Bo Zhang, Jun Yang, Mingoo Seok
2022	J	`jnl`	More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. Bo Liu, Hao Cai, Zilong Zhang, Xiaoling Ding, Ziyu Wang, Yu Gong, Weiqiang Liu, Jinjiang Yang, Zhen Wang, Jun Yang
2022	J	`jnl`	Optimal Edge Nodes Deployment With Multi Association for Smart Health. IEEE Trans. Mol. Biol. Multi Scale Commun. Chao Chen, Peng Li, Xin Jian, Langyun Wu, Jun Yang
2022	J	`jnl`	Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell. IEEE Trans. Circuits Syst. I Regul. Pap. Hao Cai, Yanan Guo, Bo Liu, Mingyang Zhou, Juntong Chen, Xinning Liu, Jun Yang
2022	J	`jnl`	SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU. IEEE J. Solid State Circuits Xinning Liu, Xiaomin Li, Huanqing Zhang, Chenyang Li, Lizheng Ren, Qing Chen, Yibo Xu, Jun Yang
2022	C	`conf`	SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation. ISCAS Bo Wang, Chen Xue, Han Liu, Xiang Li, Anran Yin, Zhongyuan Feng, Yuyao Kong, Tianzhu Xiong, Haiming Hsu, Yongliang Zhou, An Guo, Yufei Wang, Jun Yang, Xin Si
2022	J	`jnl`	Self-compensation tensor multiplication unit for adaptive approximate computing in low-power CNN processing. Sci. China Inf. Sci. Bo Liu, Zilong Zhang, Hao Cai, Reyuan Zhang, Zhen Wang, Jun Yang
2022	C	`conf`	ShareFloat CIM: A Compute-In-Memory Architecture with Floating-Point Multiply-and-Accumulate Operations. ISCAS An Guo, Yongliang Zhou, Bo Wang, Tianzhu Xiong, Chen Xue, Yufei Wang, Xin Si, Jun Yang
2022	J	`jnl`	SmartFPS: Neural Network based Wireless-inertial fusion positioning system. CoRR Luchi Hua, Jun Yang
2022	—	`conf`	TICA: A 0.3V, Variation-Resilient 64-Stage Deeply-Pipelined Bitcoin Mining Core with Timing Slack Inference and Clock Frequency Adaption. CICC Jieyu Li, Weifeng He, Bo Zhang, Guanghui He, Jun Yang, Mingoo Seok
2022	A	`conf`	Triple-Skipping Near-MRAM Computing Framework for AIoT Era. DATE Juntong Chen, Hao Cai, Bo Liu, Jun Yang
2021	—	`conf`	29.8 115nA@3V ULPMark-CP Score 1205 SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU. ISSCC Xiaomin Li, Yibo Xu, Lizheng Ren, Weiwei Ge, Jianlong Cai, Xinning Liu, Jun Yang
2021	J	`jnl`	A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS. IEEE J. Solid State Circuits Weiwei Shan, Minhao Yang, Tao Wang, Yicheng Lu, Hao Cai, Lixuan Zhu, Jiaming Xu, Chengjun Wu, Longxing Shi, Jun Yang
2021	J	`jnl`	A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages. IEEE Trans. Very Large Scale Integr. Syst. Ming Ling, Qingde Lin, Ke Tan, Tianxiang Shao, Shan Shen, Jun Yang
2021	J	`jnl`	A survey of in-spin transfer torque MRAM computing. Sci. China Inf. Sci. Hao Cai, Bo Liu, Juntong Chen, Lirida A. B. Naviner, Yongliang Zhou, Zhen Wang, Jun Yang
2021	—	`conf`	An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOS. A-SSCC Ziyu Li, Weiwei Shan, Chengjun Wu, Haitao Ge, Jun Yang
2021	—	`conf`	Challenge and Trend of SRAM Based Computation-in-Memory Circuits for AI Edge Devices. ASICON Xin Si, Yongliang Zhou, Jun Yang, Meng-Fan Chang
2021	—	`conf`	Cryogenic In-MRAM Computing. NANOARCH Yaoru Hou, We Ge, Yanan Guo, Lirida A. B. Naviner, You Wang, Bo Liu, Jun Yang, Hao Cai
2021	—	`conf`	Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices. ISOCC Tianzhu Xiong, Yongliang Zhou, Yuyao Kong, Bo Wang, An Guo, Yufei Wang, Chen Xue, Haiming Hsu, Xin Si, Jun Yang
2021	J	`jnl`	FusionVLP: The Fusion of Photodiode and Camera for Visible Light Positioning. IEEE Trans. Veh. Technol. Luchi Hua, Yuan Zhuang, You Li, Qin Wang, Bingpeng Zhou, Longning Qi, Jun Yang, Yue Cao, Harald Haas
2021	J	`jnl`	Proposal of Analog In-Memory Computing with Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell. CoRR Hao Cai, Yanan Guo, Bo Liu, Mingyang Zhou, Juntong Chen, Xinning Liu, Jun Yang
2021	J	`jnl`	Semi-Analytical Path Delay Variation Model With Adjacent Gates Decorrelation for Subthreshold Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jingjing Guo, Peng Cao, Mengxiao Li, Yu Gong, Zhiyuan Liu, Geng Bai, Jun Yang
2021	J	`jnl`	TIMAQ: A Time-Domain Computing-in-Memory-Based Processor Using Predictable Decomposed Convolution for Arbitrary Quantized DNNs. IEEE J. Solid State Circuits Jianxun Yang, Yuyao Kong, Zhao Zhang, Zhuangzhi Liu, Jing Zhou, Yiqi Wang, Yonggang Liu, Chenfu Guo, Te Hu, Congcong Li, Leibo Liu, Jin Zhang, Shaojun Wei, Jun Yang, Shouyi Yin
2020	—	`conf`	14.1 A 510nW 0.41V Low-Memory Low-Computation Keyword-Spotting Chip Using Serial FFT-Based MFCC and Binarized Depthwise Separable Convolutional Neural Network in 28nm CMOS. ISSCC Weiwei Shan, Minhao Yang, Jiaming Xu, Yicheng Lu, Shuai Zhang, Tao Wang, Jun Yang, Longxing Shi, Mingoo Seok
2020	J	`jnl`	A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor. IEEE Trans. Circuits Syst. Bo Liu, Hao Cai, Zhen Wang, Yuhao Sun, Zeyu Shen, Wentao Zhu, Yan Li, Yu Gong, Wei Ge, Jun Yang, Longxing Shi
2020	J	`jnl`	A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System. IEEE J. Solid State Circuits Weiwei Shan, Wentao Dai, Liang Wan, Minyi Lu, Longxing Shi, Mingoo Seok, Jun Yang
2020	J	`jnl`	A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. Yongliang Zhou, Hao Cai, Lei Xie, Menglin Han, Mingyue Liu, Shi Xu, Bo Liu, Weisheng Zhao, Jun Yang
2020	—	`conf`	A Time-Domain Computing-in-Memory based Processor using Predictable Decomposed Convolution for Arbitrary Quantized DNNs. A-SSCC Jianxun Yang, Yuyao Kong, Zhao Zhang, Zhuangzhi Liu, Jing Zhou, Yiqi Wang, Yonggang Liu, Chenfu Guo, Te Hu, Congcong Li, Leibo Liu, Jin Zhang, Shaojun Wei, Jun Yang, Shouyi Yin
2020	J	`jnl`	Bandwidth-Enhanced Oversampling Successive Approximation Readout Technique for Low-Noise Power-Efficient MEMS Capacitive Accelerometer. IEEE J. Solid State Circuits Longjie Zhong, Jun Yang, Donglai Xu, Xinquan Lai
2020	A*	`conf`	CATCAM: Constant-time Alteration Ternary CAM with Scalable In-Memory Architecture. MICRO Dibei Chen, Zhaoshi Li, Tianzhu Xiong, Zhiwei Liu, Jun Yang, Shouyi Yin, Shaojun Wei, Leibo Liu
2020	J	`jnl`	MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing. IEEE Trans. Circuits Syst. Yongliang Zhou, Hao Cai, Bo Liu, Weisheng Zhao, Jun Yang
2020	J	`jnl`	Machine Learning Assisted Side-Channel-Attack Countermeasure and Its Application on a 28-nm AES Circuit. IEEE J. Solid State Circuits Weiwei Shan, Shuai Zhang, Jiaming Xu, Minyi Lu, Longxing Shi, Jun Yang
2020	A	`conf`	Modeling and Designing of a PVT Auto-tracking Timing-speculative SRAM. DATE Shan Shen, Tianxiang Shao, Ming Ling, Jun Yang, Longxing Shi
2020	—	`conf`	Power-Efficient Approximate Multiplier Using Adaptive Error Compensation. ACM Great Lakes Symposium on VLSI Zhixi Yang, Honglan Jiang, Xianbin Li, Jun Yang
2020	C	`conf`	Statistical Timing Model for Subthreshold Circuit with Correlated Variation Consideration. ISCAS Jingjing Guo, Peng Cao, Mengxiao Li, Zhiyuan Liu, Jun Yang
2020	J	`jnl`	TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS. IEEE J. Solid State Circuits Weiwei Shan, Wentao Dai, Chuan Zhang, Hao Cai, Peiye Liu, Jun Yang, Longxing Shi
2020	J	`jnl`	TS Cache: A Fast Cache With Timing-Speculation Mechanism Under Low Supply Voltages. IEEE Trans. Very Large Scale Integr. Syst. Shan Shen, Tianxiang Shao, Xiaojing Shang, Yichen Guo, Ming Ling, Jun Yang, Longxing Shi
2020	J	`jnl`	Towards an automated design flow for memristor based VLSI circuits. Integr. Lei Xie, Hao Cai, Chao Wang, Jun Yang
2019	—	`conf`	A 923 Gbps/W, 113-Cycle, 2-Sbox Energy-efficient AES Accelerator in 28nm CMOS. VLSI Circuits Weiwei Shan, Ao Fan, Jiaming Xu, Jun Yang, Mingoo Seok
2019	J	`jnl`	A Review of Sparse Recovery Algorithms. IEEE Access Elaine Crespo Marques, Nilson Maciel, Lirida A. B. Naviner, Hao Cai, Jun Yang
2019	—	`conf`	A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement. NANOARCH Yongliang Zhou, Menglin Han, Mingyue Liu, Hao Cai, Bo Liu, Jun Yang
2019	—	`conf`	A Statistical Current and Delay Model Based on Log-Skew-Normal Distribution for Low Voltage Region. ACM Great Lakes Symposium on VLSI Peng Cao, Jiangping Wu, Zhiyuan Liu, Jingjing Guo, Jun Yang, Longxing Shi
2019	A	`conf`	A Statistical Timing Model for Low Voltage Design Considering Process Variation. ICCAD Peng Cao, Zhiyuan Liu, Jiangping Wu, Jingjing Guo, Jun Yang, Longxing Shi
2019	J	`jnl`	A Wide-Voltage-Range Half-Path Timing Error-Detection System With a 9-Transistor Transition-Detector in 40-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Weiwei Shan, Xinchao Shang, Xing Wan, Hao Cai, Chuan Zhang, Jun Yang
2019	—	`conf`	Accurate and Efficient Interdependent Timing Model for Flip-Flop in Wide Voltage Region. NEWCAS Peng Cao, Zhiyuan Liu, Jingjing Guo, Haoyu Pang, Jiangping Wu, Jun Yang
2019	J	`jnl`	Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration. IEEE Trans. Circuits Syst. I Regul. Pap. Hao Cai, You Wang, Lirida Alves de Barros Naviner, Xinning Liu, Weiwei Shan, Jun Yang, Weisheng Zhao
2019	J	`jnl`	An energy-efficient voice activity detector using deep neural networks and approximate computing. Microelectron. J. Bo Liu, Zhen Wang, Shisheng Guo, Huazhen Yu, Yu Gong, Jun Yang, Longxing Shi
2019	—	`conf`	Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM. NANOARCH Mingyue Liu, Hao Cai, Menglin Han, Lei Xie, Jun Yang, Lirida A. B. Naviner
2019	J	`jnl`	Correlation of Gut Microbiome Between ASD Children and Mothers and Potential Biomarkers for Risk Assessment. Genom. Proteom. Bioinform. Ning Li, Junjie Yang, Jiaming Zhang, Cheng Liang, Ying Wang, Bin Chen, Changying Zhao, Jingwen Wang, Guangye Zhang, Dongmei Zhao, Yi Liu, Lehai Zhang, Jun Yang, Guimei Li, Zhongtao Gai, Lei Zhang, Guoping Zhao
2019	C	`conf`	Deep Learning Approaches for Sparse Recovery in Compressive Sensing. ISPA Elaine Crespo Marques, Nilson Maciel, Lirida A. B. Naviner, Hao Cai, Jun Yang
2019	—	`conf`	In-memory Processing based on Time-domain Circuit. ACM Great Lakes Symposium on VLSI Yuyao Kong, Jun Yang
2019	J	`jnl`	Low-Power Centimeter-Level Localization for Indoor Mobile Robots Based on Ensemble Kalman Smoother Using Received Signal Strength. IEEE Internet Things J. Yuan Zhuang, Qin Wang, Min Shi, Pan Cao, Longning Qi, Jun Yang
2019	J	`jnl`	Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM. IEEE Access Ming Ling, Xiaojing Shang, Shan Shen, Tianxiang Shao, Jun Yang
2019	—	`conf`	Nonlinear Functions in Learned Iterative Shrinkage-Thresholding Algorithm for Sparse Signal Recovery. SiPS Elaine Crespo Marques, Nilson Maciel, Lirida A. B. Naviner, Hao Cai, Jun Yang
2019	—	`conf`	Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction. ISVLSI Hao Cai, Honglan Jiang, Menglin Han, Zhaohao Wang, You Wang, Jun Yang, Jie Han, Leibo Liu, Weisheng Zhao
2019	—	`conf`	REAL: Logic and Arithmetic Operations Embedded in RRAM for General-Purpose Computing. NANOARCH Lei Xie, Hao Cai, Jun Yang
2019	—	`conf`	RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism. MEMSYS Xiaojing Shang, Ming Ling, Shan Shen, Tianxiang Shao, Jun Yang
2019	—	`conf`	Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation. ISSCC Jun Yang, Yuyao Kong, Zhen Wang, Yan Liu, Bo Wang, Shouyi Yin, Longxin Shi
2019	J	`jnl`	TS Cache: A Fast Cache with Timing-speculation Mechanism Under Low Supply Voltages. CoRR Shan Shen, Tianxiang Shao, Xiaojing Shang, Yichen Guo, Ming Ling, Jun Yang, Longxing Shi
2019	J	`jnl`	The Integration of Photodiode and Camera for Visible Light Positioning by Using Fixed-Lag Ensemble Kalman Smoother. Remote. Sens. Yuan Zhuang, Qin Wang, You Li, Zhouzheng Gao, Bingpeng Zhou, Longning Qi, Jun Yang, Ruizhi Chen, Naser El-Sheimy
2019	J	`jnl`	Visible Light Positioning and Navigation Using Noise Measurement and Mitigation. IEEE Trans. Veh. Technol. Yuan Zhuang, Luchi Hua, Qin Wang, Yue Cao, Zhouzheng Gao, Longning Qi, Jun Yang, John Thompson
2019	—	`conf`	Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI. ACM Great Lakes Symposium on VLSI Hao Cai, Menglin Han, Weiwei Shan, Jun Yang, You Wang, Wang Kang, Weisheng Zhao
2018	—	`conf`	A 0.46V-1.1V Transition-Detector with In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in AES Accelerator. A-SSCC Xinchao Shang, Weiwei Shan, Jiaming Xu, Minyi Lu, Yiming Xiang, Longxing Shi, Jun Yang
2018	J	`jnl`	A Double Dwell High Sensitivity GPS Acquisition Scheme Using Binarized Convolution Neural Network. Sensors Zhen Wang, Yuan Zhuang, Jun Yang, Hengfeng Zhang, Wei Dong, Min Wang, Luchi Hua, Bo Liu, Longxing Shi
2018	J	`jnl`	A Double Sensing Scheme With Selective Bitline Voltage Regulation for Ultralow-Voltage Timing Speculative SRAM. IEEE J. Solid State Circuits Jun Yang, Hao Ji, Yichen Guo, Jizhe Zhu, Yuan Zhuang, Zhi Li, Xinning Liu, Longxing Shi
2018	J	`jnl`	A Low Overhead, Within-a-Cycle Adaptive Clock Stretching Circuit With Wide Operating Range in 40-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Weiwei Shan, Liang Wan, Xinning Liu, Xinchao Shang, Wentao Dai, Shuai Shao, Jun Yang, Longxing Shi
2018	J	`jnl`	A Low-Overhead Timing Monitoring Technique for Variation-Tolerant Near-Threshold Digital Integrated Circuits. IEEE Access Weiwei Shan, Xinning Liu, Minyi Lu, Liang Wan, Jun Yang
2018	J	`jnl`	A Pervasive Integration Platform of Low-Cost MEMS Sensors and Wireless Signals for Indoor Localization. IEEE Internet Things J. Yuan Zhuang, Jun Yang, Longning Qi, You Li, Yue Cao, Naser El-Sheimy
2018	—	`conf`	A Power Analysis Attack Countermeasure Based on Random Execution. TrustCom/BigDataSE Shenghua Chen, Wei Ge, Jinjiang Yang, Bo Liu, Jun Yang
2018	J	`jnl`	A Survey of Positioning Systems Using Visible LED Lights. IEEE Commun. Surv. Tutorials Yuan Zhuang, Luchi Hua, Longning Qi, Jun Yang, Pan Cao, Yue Cao, Yongpeng Wu, John Thompson, Harald Haas
2018	A*	`conf`	A fast and robust failure analysis of memory circuits using adaptive importance sampling method. DAC Xiao Shi, Fengyuan Liu, Jun Yang, Lei He
2018	—	`conf`	An Energy-efficient Reconfigurable Hybrid DNN Architecture for Speech Recognition with Approximate Computing. DSP Bo Liu, Shisheng Guo, Hai Qin, Yu Gong, Jinjiang Yang, Wei Ge, Jun Yang
2018	J	`jnl`	An improved BIJM circuit based on undersampling technique. IEICE Electron. Express Zhikuang Cai, Haobo Xu, Jian Xiao, Jun Yang
2018	—	`conf`	Compressed Sensing for Wideband HF Channel Estimation. ICFSP Elaine Crespo Marques, Nilson Maciel, Lirida A. B. Naviner, Hao Cai, Jun Yang
2018	—	`conf`	Design and Optimization of Reconfigurable Data Path for Communication Baseband Signal Processing. CyberC Shan-shan Zhu, Hai Qin, Bo Liu, Jun Yang
2018	J	`jnl`	EERA-DNN: An energy-efficient reconfigurable architecture for DNNs with hybrid bit-width and logarithmic multiplier. IEICE Electron. Express Zhen Wang, Mengwen Xia, Bo Liu, Xing Ruan, Yu Gong, Jinjiang Yang, Wei Ge, Jun Yang
2018	C	`conf`	Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques. ISCAS Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner, Weiwei Shan, Jun Yang, Weisheng Zhao
2018	J	`jnl`	Guest Editorial: Special Issue on Toward Positioning, Navigation, and Location-Based Services (PNLBS) for Internet of Things. IEEE Internet Things J. Yuan Zhuang, Yue Cao, Naser El-Sheimy, Jun Yang
2018	J	`jnl`	HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs. IEEE Trans. Circuits Syst. I Regul. Pap. Wentao Dai, Weiwei Shan, Xinchao Shang, Xinning Liu, Hao Cai, Jun Yang
2018	—	`conf`	MRAM-on-FDSOI Integration: A Bit-Cell Perspective. ISVLSI Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner, Xinning Liu, Jun Yang, Weisheng Zhao
2018	J	`jnl`	Noise Analysis and Modeling in Visible Light Communication Using Allan Variance. IEEE Access Luchi Hua, Yuan Zhuang, Longning Qi, Jun Yang, Longxing Shi
2018	—	`conf`	Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power. DCIS Hao Cai, Menglin Han, You Wang, Lirida A. B. Naviner, Xinning Liu, Jun Yang, Weisheng Zhao
2018	—	`conf`	Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement. APCCAS Menglin Han, Hao Cai, Jun Yang, Lirida A. B. Naviner, You Wang, Weisheng Zhao
2018	J	`jnl`	Timing Error Prediction AVFS With Detection Window Tuning for Wide-Operating-Range ICs. IEEE Trans. Circuits Syst. II Express Briefs Weiwei Shan, Xinchao Shang, Longxing Shi, Wentao Dai, Jun Yang
2017	—	`conf`	A 0.44V-1.1V 9-transistor transition-detector and half-path error detection technique for low power applications. A-SSCC Xinchao Shang, Weiwei Shan, Longxing Shi, Xing Wan, Jun Yang
2017	—	`conf`	An energy-efficient accelerator for hybrid bit-width DNNs. SSCI Bo Liu, Xing Ruan, Mengwen Xia, Yu Gong, Jinjiang Yang, Wei Ge, Jun Yang
2017	J	`jnl`	An improved timing error prediction monitor for wide adaptive frequency scaling. IEICE Electron. Express Weiwei Shan, Xinning Liu, Minyi Lu, Shuai Shao, Zhikuang Cai, Jun Yang
2017	—	`conf`	Analytical hold timing fixing for sub-threshold circuit based on its lognormal distribution. PATMOS Jingjing Guo, Min Wang, Jizhe Zhu, Xinning Liu, Jun Yang
2017	J	`jnl`	Analytical inverter chain's delay and its variation model for sub-threshold circuits. IEICE Electron. Express Jingjing Guo, Jizhe Zhu, Min Wang, Jianxin Nie, Xinning Liu, Wei Ge, Jun Yang
2017	J	`jnl`	Coarse-grained reconfigurable architecture with hierarchical context cache structure and management approach. IEICE Electron. Express Chao Wang, Peng Cao, Bo Liu, Jun Yang
2017	J	`jnl`	Context Management Scheme Optimization of Coarse-Grained Reconfigurable Architecture for Multimedia Applications. IEEE Trans. Very Large Scale Integr. Syst. Peng Cao, Bo Liu, Jinjiang Yang, Jun Yang, Meng Zhang, Longxing Shi
2017	J	`jnl`	Efficient AES cipher on coarse-grained reconfigurable architecture. IEICE Electron. Express Chao Wang, Peng Cao, Jun Yang
2017	—	`conf`	HTD: A light-weight holosymmetrical transition detector based in-situ timing monitoring technique for wide-voltage-range in 40nm CMOS. A-SSCC Wentao Dai, Weiwei Shan, Xinning Liu, Jun Yang
2017	J	`jnl`	In-Situ Timing Monitor-Based Adaptive Voltage Scaling System for Wide-Voltage-Range Applications. IEEE Access Weiwei Shan, Longxing Shi, Jun Yang
2017	—	`conf`	Processing LSTM in memory using hybrid network expansion model. SiPS Yu Gong, Tingting Xu, Bo Liu, Wei Ge, Jinjiang Yang, Jun Yang, Longxing Shi
2016	J	`jnl`	An area-efficient design of reconfigurable S-box for parallel implementation of block ciphers. IEICE Electron. Express Jinjiang Yang, Ge Wei, Peng Cao, Jun Yang
2016	J	`jnl`	High performance and area efficiency design of global register file for coarse-grained reconfigurable cryptographic processor. IEICE Electron. Express Ge Wei, Jinjiang Yang, Jun Yang
2016	J	`jnl`	Smartphone-Based Indoor Localization with Bluetooth Low Energy Beacons. Sensors Yuan Zhuang, Jun Yang, You Li, Longning Qi, Naser El-Sheimy
2015	J	`jnl`	A GPS Bit Synchronization Method Based on Frequency Compensation. IEICE Trans. Commun. Xinning Liu, Yuxiang Niu, Jun Yang, Peng Cao
2015	J	`jnl`	An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding. IEEE Trans. Multim. Leibo Liu, Dong Wang, Min Zhu, Yansheng Wang, Shouyi Yin, Peng Cao, Jun Yang, Shaojun Wei
2015	J	`jnl`	Correction to "An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding". IEEE Trans. Multim. Leibo Liu, Dong Wang, Min Zhu, Yansheng Wang, Shouyi Yin, Peng Cao, Jun Yang, Shaojun Wei
2014	A*	`conf`	A Side-channel Analysis Resistant Reconfigurable Cryptographic Coprocessor Supporting Multiple Block Cipher Algorithms. DAC Weiwei Shan, Longxing Shi, Xingyuan Fu, Xiao Zhang, Chaoxuan Tian, Zhipeng Xu, Jun Yang, Jie Li
2014	J	`jnl`	An improved memory system simulator based on DRAMSim2. IEICE Electron. Express Zhen Xie, Yang Zhang, Jun Yang, Longxing Shi
2014	J	`jnl`	On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time. IEEE Trans. Very Large Scale Integr. Syst. Yansheng Wang, Leibo Liu, Shouyi Yin, Min Zhu, Peng Cao, Jun Yang, Shaojun Wei
2013	J	`jnl`	Exploration of Full HD Media Decoding on a Software Defined Radio Baseband Processor. IEEE Trans. Signal Process. Chen Mei, Min Li, Peng Cao, Amir Amin, Chunshu Li, Jun Yang, Antoine Dejonghe, Liesbet Van der Perre, Longxing Shi, Sofie Pollin
2013	J	`jnl`	Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip. IEICE Trans. Inf. Syst. Hung K. Nguyen, Peng Cao, Xuexiang Wang, Jun Yang, Longxing Shi, Min Zhu, Leibo Liu, Shaojun Wei
2013	J	`jnl`	Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture. Sci. China Inf. Sci. Yansheng Wang, Leibo Liu, Shouyi Yin, Min Zhu, Peng Cao, Jun Yang, Shaojun Wei
2013	J	`jnl`	Implementation of correlation power analysis attack on an FPGA DES design. Int. J. Inf. Commun. Technol. Jun Yang, Weiwei Shan, Junyin Liu, Huafang Sun
2013	J	`jnl`	On-chip long-term jitter measurement for PLL based on undersampling technique. IEICE Electron. Express Zhikuang Cai, Haobo Xu, Shixuan Que, Weiwei Shan, Jun Yang
2013	J	`jnl`	Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC. IEICE Trans. Inf. Syst. Gugang Gao, Peng Cao, Jun Yang, Longxing Shi
2013	J	`jnl`	The Organization of On-Chip Data Memory in One Coarse-Grained Reconfigurable Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yansheng Wang, Leibo Liu, Shouyi Yin, Min Zhu, Peng Cao, Jun Yang, Shaojun Wei
2012	—	`conf`	Exploration of Full HD Media Decoding on SDR Baseband Processor. SiPS Chen Mei, Min Li, Peng Cao, Amir Amin, Chunshu Li, Sofie Pollin, Jun Yang
2012	J	`jnl`	Fast AdaBoost-Based Face Detection System on a Dynamically Coarse Grain Reconfigurable Architecture. IEICE Trans. Inf. Syst. Jian Xiao, Jinguo Zhang, Min Zhu, Jun Yang, Longxing Shi
2012	J	`jnl`	Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications. IEICE Trans. Inf. Syst. Bo Liu, Peng Cao, Min Zhu, Jun Yang, Leibo Liu, Shaojun Wei, Longxing Shi
2011	J	`jnl`	A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique. IEEE Trans. Very Large Scale Integr. Syst. Xin Chen, Jun Yang, Longxing Shi
2009	J	`jnl`	Analysis of Jitter in CMOS Ring Oscillators due to Power Supply Noise. IEICE Trans. Electron. Xiaoying Deng, Xin Chen, Jun Yang, Jianhui Wu
2009	A	`conf`	Area-efficient line-based two-dimensional discrete wavelet transform architecture without data buffer. ICME Peng Cao, Chao Wang, Jun Yang, Longxing Shi
2009	J	`jnl`	Extended Control Flow Graph Based Performance and Energy Consumption Optimization Using Scratch-Pad Memory. J. Circuits Syst. Comput. Xuexiang Wang, Hanlai Pu, Jun Yang, Longxing Shi
2008	J	`jnl`	A Novel Fast-Lock-in Digitally Controlled Phase-Locked Loop. IEICE Trans. Electron. Xin Chen, Jun Yang, Longxing Shi
2005	—	`conf`	Bus Buffer Evaluation of Different Arbitration Algorithms. SoCC Xufan Wu, Jun Yang, Longxing Shi
2005	—	`conf`	Domain Strategy and Coverage Metric for Validation. ISQED Chun Luo, Jun Yang, Longxing Shi, Xufan Wu, Yu Zhang
2005	—	`conf`	Domain fault model and coverage metric for SoC verification. ISCAS (6) Chun Luo, Jun Yang, Gugang Gao, Longxing Shi