Jun Yan

18 papers A 1B 3Misc 1Journal 12Unranked 1
YearRankTypeTitle / Venue / Authors
2016 J jnl
Priority L2 cache design for time predictability.
Int. J. Embed. Syst.
Jun Yan, Wei Zhang
2012 J jnl
Static Timing Analysis of Shared Caches for Multicore Processors.
J. Comput. Sci. Eng.
Wei Zhang, Jun Yan
2011 J jnl
An Interference Matrix Based Approach to Bounding Worst-Case Inter-Thread Cache Interferences and WCET for Multi-Core Processors.
J. Comput. Sci. Eng.
Jun Yan, Wei Zhang
2011 J jnl
Bounding Worst-Case Performance for Multi-Core Processors with Shared L2 Instruction Caches.
J. Comput. Sci. Eng.
Jun Yan, Wei Zhang
2011 J jnl
Computing and Reducing Transient Error Propagation in Registers.
J. Comput. Sci. Eng.
Jun Yan, Wei Zhang
2010 J jnl
Design and implementation of hybrid multicore simulators.
Int. J. Embed. Syst.
Jun Yan, Wei Zhang
2010 B conf
Time-Predictable L2 Cache Design for High-Performance Real-Time Systems.
RTCSA
Jun Yan, Wei Zhang
2009 B conf
Accurately Estimating Worst-Case Execution Time for Multi-core Processors with Shared Direct-Mapped Instruction Caches.
RTCSA
Wei Zhang, Jun Yan
2009 J jnl
Optimizing Instruction Prefetching to Improve Worst-Case Performance for Real-Time Applications.
J. Comput. Sci. Eng.
Yiqiang Ding, Jun Yan, Wei Zhang
2008 J jnl
A time-predictable VLIW processor and its compiler support.
Real Time Syst.
Jun Yan, Wei Zhang
2008 J jnl
Analyzing the worst-case execution time for instruction caches with prefetching.
ACM Trans. Embed. Comput. Syst.
Jun Yan, Wei Zhang
2008 J jnl
Exploiting virtual registers to reduce pressure on real registers.
ACM Trans. Archit. Code Optim.
Jun Yan, Wei Zhang
2008 A conf
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches.
IEEE Real-Time and Embedded Technology and Applications Symposium
Jun Yan, Wei Zhang
2007 J jnl
Evaluating instruction cache vulnerability to transient errors.
SIGARCH Comput. Archit. News
Jun Yan, Wei Zhang
2007 J jnl
Hybrid multi-core architecture for boosting single-threaded performance.
SIGARCH Comput. Archit. News
Jun Yan, Wei Zhang
2007 — conf
Virtual Registers: Reducing Register Pressure Without Enlarging the Register File.
HiPEAC
Jun Yan, Wei Zhang
2007 B conf
WCET analysis of instruction caches with prefetching.
LCTES
Jun Yan, Wei Zhang
2005 Misc conf
Compiler-guided register reliability improvement against soft errors.
EMSOFT
Jun Yan, Wei Zhang