Jun Shiomi - RankMe

59 papers A* 1B 2Misc 1Journal 22Unranked 32

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	29.5 A Sub-Gram Individual Plant Stress Sensor Tag for Smart Farming. ISSCC Daiki Nitto, Keishi Yanase, Yui Fujisawa, Jun Shiomi, Yoshihiro Midoh, Takuya Wadatsumi, Makoto Nagata, Ahmet Öncü, Constantine Sideris, Chetphilin Suriyasak, Yushi Ishibashi, Noriyuki Miura
2026	—	`conf`	PrometheusFree: Concurrent Detection of Laser Fault Injection Attacks in Optical Neural Networks. ASP-DAC Kota Nishida, Yoshihiro Midoh, Noriyuki Miura, Satoshi Kawakami, Alex Orailoglu, Jun Shiomi
2025	—	`conf`	20.1 A 3.5×3.5mm ISSCC Kotaro Naruse, Naru Kato, Takuma Matsumori, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose, Gaku Imamura, Genki Yoshikawa, Constantine Sideris, Noriyuki Miura
2025	—	`conf`	Cryo-HT: Hardware Trojan Activated at Cryogenic Temperatures. ASP-DAC Ayano Takaya, Ryuichi Nakajima, Jun Shiomi, Michihiro Shintani
2025	—	`conf`	Hardware Trojan Detection by Fine-grained Power Domain Partitioning. ASP-DAC Takahiro Ishikawa, Kose Yokooji, Yoshihiro Midoh, Noriyuki Miura, Michihiro Shintani, Jun Shiomi
2025	—	`conf`	Physical/Machine-Learning Attacks Resilient Multi-Factor Authentication Employing Handwritten Challenge into Touch-Sensor PUF. WIFS Ruochen Wang, Kosuke Kawamura, Jun Shiomi, Yoshihiro Midoh, Yuichi Tanaka, Minoru Kuribayashi, Noriyuki Miura
2024	J	`jnl`	A Robust and Energy Efficient Hyperdimensional Computing System for Voltage-scaled Circuits. ACM Trans. Embed. Comput. Syst. Dehua Liang, Hiromitsu Awano, Noriyuki Miura, Jun Shiomi
2024	—	`conf`	Edge-Oriented Point Cloud Compression by Moving Object Detection for Realtime Smart Monitoring. CCNC Itsuki Takada, Daiki Nitto, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi, Ryoichi Shinkuma
2024	B	`conf`	Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits. ASPDAC Kazuki Minamiguchi, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi
2024	J	`jnl`	SecONN: An Optical Neural Network Framework with Concurrent Detection of Thermal Fault Injection Attacks. CoRR Kota Nishida, Yoshihiro Midoh, Noriyuki Miura, Satoshi Kawakami, Jun Shiomi
2024	Misc	`conf`	Square-Wave Defined Pulse Generator for High Fidelity Gate Operation of Superconducting Qubits. QCE Ryosuke Matsuo, Kazuhisa Ogawa, Hidehisa Shiorni, Makoto Negoro, Ryutaro Ohira, Takefumi Miyoshi, Michihiro Shintani, Hiromitsu Awano, Takashi Sato, Jun Shiomi
2024	J	`jnl`	StrideHD: A Binary Hyperdimensional Computing System Utilizing Window Striding for Image Classification. IEEE Open J. Circuits Syst. Dehua Liang, Jun Shiomi, Noriyuki Miura, Hiromitsu Awano
2023	—	`conf`	A Self-Programming PUF Harvesting the High-Energy Plasma During Fabrication. ISSCC Kotaro Naruse, Takayuki Ueda, Jun Shiomi, Yoshihiro Midoh, Noriyuki Miura
2023	—	`conf`	A Triturated Sensing System. ISSCC Noriyuki Miura, Kotaro Naruse, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose, Takaaki Okidono, Takuji Miki, Makoto Nagata
2023	J	`jnl`	Approximation-Based System Implementation for Real-Time Minimum Energy Point Tracking over a Wide Operating Performance Region. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera
2023	—	`conf`	DependableHD: A Hyperdimensional Learning Framework for Edge-Oriented Voltage-Scaled Circuits. ASP-DAC Dehua Liang, Hiromitsu Awano, Noriyuki Miura, Jun Shiomi
2023	J	`jnl`	Nonvolatile Storage Cells Using FiCC for IoT Processors with Intermittent Operations. IEICE Trans. Electron. Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi
2022	J	`jnl`	A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter. IEICE Trans. Inf. Syst. Dehua Liang, Jun Shiomi, Noriyuki Miura, Masanori Hashimoto, Hiromitsu Awano
2022	J	`jnl`	Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takumi Komori, Yutaka Masuda, Jun Shiomi, Tohru Ishihara
2022	—	`conf`	Approximation-Based Implementation for a Minimum Energy Point Tracking Algorithm over a Wide Operating Performance Region. LASCAS Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera
2022	—	`conf`	DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification. ASP-DAC Dehua Liang, Jun Shiomi, Noriyuki Miura, Hiromitsu Awano
2022	B	`conf`	Real-time adaptive data filtering with multiple sensors for indoor monitoring. NOMS Kuon Akiyama, Ryoichi Shinkuma, Jun Shiomi
2022	—	`conf`	Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits. SOCC Jun Shiomi, Shogo Terada, Tohru Ishihara, Hidetoshi Onodera
2022	—	`conf`	Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations. COOL CHIPS Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi
2021	J	`jnl`	A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation. IEICE Trans. Electron. Kentaro Nagai, Jun Shiomi, Hidetoshi Onodera
2021	J	`jnl`	A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
2021	J	`jnl`	Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hongjie Xu, Jun Shiomi, Hidetoshi Onodera
2021	—	`conf`	Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing. ISQED Takumi Komori, Yutaka Masuda, Jun Shiomi, Tohru Ishihara
2021	J	`jnl`	MOSDA: On-Chip Memory Optimized Sparse Deep Neural Network Accelerator With Efficient Index Matching. IEEE Open J. Circuits Syst. Hongjie Xu, Jun Shiomi, Hidetoshi Onodera
2021	J	`jnl`	Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Naoki Hattori, Jun Shiomi, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi
2021	J	`jnl`	Supply and Threshold Voltage Scaling for Minimum Energy Operation over a Wide Operating Performance Region. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera
2021	A*	`conf`	Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics. DAC Jun Shiomi, Shuya Kotsugi, Boyu Dong, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
2020	—	`conf`	A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias. APCCAS Kentaro Nagai, Jun Shiomi, Hidetoshi Onodera
2020	—	`conf`	A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing. ISVLSI Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
2020	—	`conf`	An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics. ICRC Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
2020	—	`conf`	Dynamic Supply and Threshold Voltage Scaling towards Runtime Energy Optimization over a Wide Operating Performance Region. SoCC Shoya Sonoda, Jun Shiomi, Hidetoshi Onodera
2020	—	`conf`	On-chip Memory Optimized CNN Accelerator with Efficient Partial-sum Accumulation. ACM Great Lakes Symposium on VLSI Hongjie Xu, Jun Shiomi, Hidetoshi Onodera
2020	—	`conf`	Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy. ISVLSI Khyati Kiyawat, Yutaka Masuda, Jun Shiomi, Tohru Ishihara
2019	J	`jnl`	A Design Method of a Cell-Based Amplifier for Body Bias Generation. IEICE Trans. Electron. Takuya Koyanagi, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2019	—	`conf`	An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator. PHOTONICS@SC Tohru Ishihara, Jun Shiomi, Naoki Hattori, Yutaka Masuda, Akihiko Shinya, Masaya Notomi
2019	J	`jnl`	Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing. Integr. Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2019	—	`conf`	BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing. ASP-DAC Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
2019	J	`jnl`	Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
2019	J	`jnl`	On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2018	—	`conf`	An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing. ICRC Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi
2018	—	`conf`	Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure. PATMOS Hongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2018	J	`jnl`	Minimum Energy Point Tracking with All-Digital On-Chip Sensors. J. Low Power Electron. Jun Shiomi, Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera
2017	J	`jnl`	A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2017	—	`—`	Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits. Jun Shiomi
2017	—	`conf`	Pin accessibility evaluating model for improving routability of VLSI designs. SoCC Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera
2016	—	`conf`	A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region. ASP-DAC Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2016	J	`jnl`	Analytical Stability Modeling for CMOS Latches in Low Voltage Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2016	—	`conf`	Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing. PATMOS Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2016	—	`conf`	Variability- and correlation-aware logical effort for near-threshold circuit design. ISQED Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2015	—	`conf`	An energy-efficient on-chip memory structure for variability-aware near-threshold operation. ISQED Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2015	—	`conf`	Microarchitectural-level statistical timing models for near-threshold circuit design. ASP-DAC Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2015	J	`jnl`	Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2015	J	`jnl`	Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring. IEEE J. Solid State Circuits Islam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
2014	—	`conf`	Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring. A-SSCC Islam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera