Jun Lin - RankMe

183 papers A* 1A 1B 2C 24Misc 7Journal 94Unranked 54

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	WiFlow: A Precision-Scalable DNN Training Accelerator Through Winograd Algorithm and Dataflow Co-Design. IEEE Trans. Circuits Syst. I Regul. Pap. Hui Wang, Jinming Lu, Rui Ding, Weize Ma, Zhongfeng Wang, Jun Lin
2025	C	`conf`	A High-Speed 8-bit Single-Channel SAR ADC with Tailored Bit Intervals. ISCAS Xinyu Li, Ruida Wang, Mengying Zhang, Congyi Zhu, Zhongfeng Wang, Jun Lin
2025	J	`jnl`	A RISC-V Domain-Specific Processor for Deep Learning-Based Channel Estimation. IEEE Trans. Circuits Syst. I Regul. Pap. Meng Guo, Qi Wu, Chuanning Wang, Yangcan Zhou, Shaowei Wang, Chuan Zhang, Zhongfeng Wang, Jun Lin
2025	A	`conf`	AiSpGEMM: Accelerating Imbalanced SpGEMM on FPGAs with Flexible Interconnect and Intra-row Parallel Merging. DATE Enhao Tang, Shun Li, Hao Zhou, Guohao Dai, Jun Lin, Kun Wang
2025	J	`jnl`	DiffAccel: Accelerating Diffusion Models Through Adaptive Feature Optimization and Dynamic Hardware Adaptation. IEEE Trans. Very Large Scale Integr. Syst. Enhao Tang, Weize Ma, Yudan Jiang, Sheng Xu, Zhongfeng Wang, Jun Lin
2025	J	`jnl`	Enable Lightweight and Precision-Scalable Posit/IEEE-754 Arithmetic in RISC-V Cores for Transprecision Computing. CoRR Qiong Li, Chao Fang, Longwei Huang, Jun Lin, Zhongfeng Wang
2025	J	`jnl`	HWSA: A High-Ratio Weight Sparse Accelerator for Efficient CNN Inference. IEEE Trans. Circuits Syst. I Regul. Pap. Xuejing Dai, Jinze Zhang, Zhongfeng Wang, Jun Lin
2025	J	`jnl`	SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multiprecision DNN Inference. IEEE Trans. Very Large Scale Integr. Syst. Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin
2024	B	`conf`	A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge. ASPDAC Longwei Huang, Chao Fang, Qiong Li, Jun Lin, Zhongfeng Wang
2024	C	`conf`	A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference. ISCAS Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin
2024	J	`jnl`	A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference. CoRR Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin
2024	J	`jnl`	Amoeba: An Efficient and Flexible FPGA-Based Accelerator for Arbitrary-Kernel CNNs. IEEE Trans. Very Large Scale Integr. Syst. Xiao Wu, Miaoxin Wang, Jun Lin, Zhongfeng Wang
2024	C	`conf`	An FPGA-Based Accelerator Enabling Efficient Support for CNNs with Arbitrary Kernel Sizes. ISCAS Miaoxin Wang, Xiao Wu, Jun Lin, Zhongfeng Wang
2024	J	`jnl`	An FPGA-Based Accelerator Enabling Efficient Support for CNNs with Arbitrary Kernel Sizes. CoRR Miaoxin Wang, Xiao Wu, Jun Lin, Zhongfeng Wang
2024	J	`jnl`	SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference. CoRR Chuanning Wang, Chao Fang, Xiao Wu, Zhongfeng Wang, Jun Lin
2024	J	`jnl`	TECO: A Unified Feature Map Compression Framework Based on Transform and Entropy. IEEE Trans. Neural Networks Learn. Syst. Yubo Shi, Meiqi Wang, Tianyu Cao, Jun Lin, Zhongfeng Wang
2024	J	`jnl`	WinTA: An Efficient Reconfigurable CNN Training Accelerator With Decomposition Winograd. IEEE Trans. Circuits Syst. I Regul. Pap. Jinming Lu, Hui Wang, Jun Lin, Zhongfeng Wang
2023	J	`jnl`	A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge. CoRR Longwei Huang, Chao Fang, Qiong Li, Jun Lin, Zhongfeng Wang
2023	J	`jnl`	An Efficient Massive MIMO Detector Based on Approximate Expectation Propagation. IEEE Trans. Very Large Scale Integr. Syst. Yangyang Chen, Suwen Song, Zhongfeng Wang, Jun Lin
2023	—	`conf`	An FPGA-Based Reconfigurable CNN Training Accelerator Using Decomposable Winograd. ISVLSI Hui Wang, Jinming Lu, Jun Lin, Zhongfeng Wang
2023	J	`jnl`	Fast and Accurate FSA System Using ELBERT: An Efficient and Lightweight BERT. IEEE Trans. Signal Process. Siyuan Lu, Chenchen Zhou, Keli Xie, Jun Lin, Zhongfeng Wang
2022	J	`jnl`	A Proximal Iteratively Reweighted Approach for Efficient Network Sparsification. IEEE Trans. Computers Hao Wang, Xiangyu Yang, Yuanming Shi, Jun Lin
2022	C	`conf`	A Reconfigurable Approach for Deconvolutional Network Acceleration with Fast Algorithm. ISCAS Peixiang Yang, Wendong Mao, Zhongfeng Wang, Jun Lin
2022	C	`conf`	Accelerate Three-Dimensional Generative Adversarial Networks Using Fast Algorithm. ISCAS Ziqi Su, Wendong Mao, Zhongfeng Wang, Jun Lin, Wenqiang Wang, Haitao Sun
2022	—	`conf`	An Efficient CNN Training Accelerator Leveraging Transposable Block Sparsity. AICAS Mingyang Xu, Jinming Lu, Zhongfeng Wang, Jun Lin
2022	—	`conf`	An Efficient FPGA Accelerator for Point Cloud. SOCC Zilun Wang, Wendong Mao, Peixiang Yang, Zhongfeng Wang, Jun Lin
2022	J	`jnl`	An Efficient FPGA Accelerator for Point Cloud. CoRR Zilun Wang, Wendong Mao, Peixiang Yang, Zhongfeng Wang, Jun Lin
2022	C	`conf`	An Efficient Hardware Accelerator for Sparse Transformer Neural Networks. ISCAS Chao Fang, Shouliang Guo, Wei Wu, Jun Lin, Zhongfeng Wang, Ming Kai Hsu, Lingzhi Liu
2022	J	`jnl`	Efficient Software Implementation of the SIKE Protocol Using a New Data Representation. IEEE Trans. Computers Jing Tian, Piaoyang Wang, Zhe Liu, Jun Lin, Zhongfeng Wang, Johann Großschädl
2022	J	`jnl`	Fast and Accurate FSA System Using ELBERT: An Efficient and Lightweight BERT. CoRR Siyuan Lu, Chenchen Zhou, Keli Xie, Shiyi Liu, Jun Lin, Zhongfeng Wang
2022	—	`conf`	Forecasting Stock Indexes with Metabolic DWT and MWA-GM(1,1). WCSP Ziyang Jiang, Siyuan Lu, Jun Lin, Zhongfeng Wang
2022	Misc	`conf`	Magical-Decomposition: Winning Both Adversarial Robustness and Efficiency on Hardware. ICMLC Xin Cheng, Meiqi Wang, Yubo Shi, Jun Lin, Zhongfeng Wang
2022	J	`jnl`	Rethinking Adaptive Computing: Building a Unified Model Complexity-Reduction Framework With Adversarial Robustness. IEEE Trans. Neural Networks Learn. Syst. Meiqi Wang, Liulu He, Jun Lin, Zhongfeng Wang
2021	J	`jnl`	An Efficient and Flexible Accelerator Design for Sparse Convolutional Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Xiaoru Xie, Jun Lin, Zhongfeng Wang, Jinghe Wei
2021	—	`conf`	An FPGA-Based Reconfigurable Accelerator for Low-Bit DNN Training. ISVLSI Haikuo Shao, Jinming Lu, Jun Lin, Zhongfeng Wang
2021	J	`jnl`	An Improved Reliability-Based Decoding Algorithm for NB-LDPC Codes. IEEE Commun. Lett. Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang
2021	—	`conf`	Automatic Generation of Dynamic Inference Architecture for Deep Neural Networks. SiPS Shize Zhao, Liulu He, Xiaoru Xie, Jun Lin, Zhongfeng Wang
2021	—	`conf`	Counter Random Gradient Descent Bit-Flipping Decoder for LDPC Codes. ISVLSI Keyue Deng, Hangxuan Cui, Jun Lin, Zhongfeng Wang
2021	J	`jnl`	Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. Hangxuan Cui, Fakhreddine Ghaffari, Khoa Le, David Declercq, Jun Lin, Zhongfeng Wang
2021	J	`jnl`	Evaluations on Deep Neural Networks Training Using Posit Number System. IEEE Trans. Computers Jinming Lu, Chao Fang, Mingyang Xu, Jun Lin, Zhongfeng Wang
2021	J	`jnl`	Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography. IEEE Trans. Very Large Scale Integr. Syst. Jing Tian, Jun Lin, Zhongfeng Wang
2021	J	`jnl`	Low-Latency Hardware Accelerator for Improved Engle-Granger Cointegration in Pairs Trading. IEEE Trans. Circuits Syst. I Regul. Pap. Shuang Liang, Siyuan Lu, Jun Lin, Zhongfeng Wang
2021	—	`conf`	PipeBSW: A Two-Stage Pipeline Structure for Banded Smith-Waterman Algorithm on FPGA. ISVLSI Luyi Li, Jun Lin, Zhongfeng Wang
2020	—	`conf`	A Computation-Efficient Solution for Acceleration of Generative Adversarial Network. NEWCAS Peixiang Yang, Wendong Mao, Jun Lin, Zhongfeng Wang
2020	—	`conf`	A Configurable FPGA Accelerator of Bi-LSTM Inference with Structured Sparsity. SoCC Shouliang Guo, Chao Fang, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	A Novel Iterative Reliability-Based Majority-Logic Decoder for NB-LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs Suwen Song, Hangxuan Cui, Jing Tian, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	A Precision-Scalable Energy-Efficient Convolutional Neural Network Accelerator. IEEE Trans. Circuits Syst. Wenjian Liu, Jun Lin, Zhongfeng Wang
2020	—	`conf`	A Reconfigurable DNN Training Accelerator on FPGA. SiPS Jinming Lu, Jun Lin, Zhongfeng Wang
2020	—	`conf`	A Serial Maximum-likelihood Detection Algorithm for Massive MIMO Systems. NEWCAS Jing Zeng, Jun Lin, Zhongfeng Wang
2020	C	`conf`	A Three-Level Scoring System for Fast Similarity Evaluation Based on Smith-Waterman Algorithm. ISCAS Yujie Zhang, Jiajun Wu, Minghao Li, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	A lightweight face detector by integrating the convolutional neural network with the image pyramid. Pattern Recognit. Lett. Jiapeng Luo, Jiaying Liu, Jun Lin, Zhongfeng Wang
2020	—	`conf`	Efficient FPGA design for Convolutions in CNN based on FFT-pruning. APCCAS Liulu He, Xiaoru Xie, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	Efficient Precision-Adjustable Architecture for Softmax Function in Deep Learning. IEEE Trans. Circuits Syst. Danyang Zhu, Siyuan Lu, Meiqi Wang, Jun Lin, Zhongfeng Wang
2020	—	`conf`	Exploring Quantization in Few-Shot Learning. NEWCAS Meiqi Wang, Ruixin Xue, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	F-DNA: Fast Convolution Architecture for Deconvolutional Network Acceleration. IEEE Trans. Very Large Scale Integr. Syst. Wendong Mao, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	Faster Software Implementation of the SIKE Protocol Based on A New Data Representation. IACR Cryptol. ePrint Arch. Jing Tian, Piaoyang Wang, Zhe Liu, Jun Lin, Zhongfeng Wang, Johann Großschädl
2020	—	`conf`	Financial Time Series Forecasting Model Based on EMD and Rolling Grey Model. SiPS Binjing Li, Fenggui Liu, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	Fine-Grained Bit-Flipping Decoding for LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs Yuxing Chen, Hangxuan Cui, Jun Lin, Zhongfeng Wang
2020	C	`conf`	Hardware Accelerator for Engle-Granger Cointegration in Pairs Trading. ISCAS Shuang Liang, Siyuan Lu, Jun Lin, Zhongfeng Wang
2020	—	`conf`	Hardware Accelerator for Multi-Head Attention and Position-Wise Feed-Forward in the Transformer. SoCC Siyuan Lu, Meiqi Wang, Shuang Liang, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	Hardware Accelerator for Multi-Head Attention and Position-Wise Feed-Forward in the Transformer. CoRR Siyuan Lu, Meiqi Wang, Shuang Liang, Jun Lin, Zhongfeng Wang
2020	—	`conf`	In-Memory Computing: The Next-Generation AI Computing Paradigm. ACM Great Lakes Symposium on VLSI Yufei Ma, Yuan Du, Li Du, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	Information Storage Bit-Flipping Decoder for LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. Hangxuan Cui, Jun Lin, Zhongfeng Wang
2020	—	`conf`	LBFP: Logarithmic Block Floating Point Arithmetic for Deep Neural Networks. APCCAS Chao Ni, Jinming Lu, Jun Lin, Zhongfeng Wang
2020	B	`conf`	LSTM-Based Quantitative Trading Using Dynamic K-Top and Kelly Criterion. IJCNN Binjing Li, Keli Xie, Siyuan Lu, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	Multi-Layer Generalized Integrated Interleaved Codes. IEEE Commun. Lett. Wenjie Li, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	Optimized Trellis-Based Min-Max Decoder for NB-LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs Jing Tian, Suwen Song, Jun Lin, Zhongfeng Wang
2020	—	`conf`	Temporal Residual Feature Learning for Efficient 3D Convolutional Neural Network on Action Recognition Task. SiPS Haonan Wang, Yuchen Mei, Jun Lin, Zhongfeng Wang
2020	J	`jnl`	Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography. IACR Cryptol. ePrint Arch. Jing Tian, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	A 124-Gb/s Decoder for Generalized Integrated Interleaved Codes. IEEE Trans. Circuits Syst. I Regul. Pap. Wenjie Li, Jun Lin, Zhongfeng Wang
2019	—	`conf`	A Decomposition Mapping based Quantized Belief Propagation Decoding for 5G LDPC Codes. ISCIT Hangxuan Cui, Khoa Le, Fakhreddine Ghaffari, David Declercq, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	A Hardware-Oriented and Memory-Efficient Method for CTC Decoding. IEEE Access Siyuan Lu, Jinming Lu, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	A Hardware-Oriented and Memory-Efficient Method for CTC Decoding. CoRR Siyuan Lu, Jinming Lu, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	A High-Speed Successive-Cancellation Decoder for Polar Codes Using Approximate Computing. IEEE Trans. Circuits Syst. II Express Briefs Yangcan Zhou, Zhiyu Chen, Jun Lin, Zhongfeng Wang
2019	—	`conf`	A Low-Complexity Error-and-Erasure Decoding Algorithm for t=2 RS Codes. SiPS Zengchao Yan, Wenjie Li, Jun Lin, Zhongfeng Wang
2019	—	`conf`	A Low-Complexity RS Decoder for Triple-Error-Correcting RS Codes. ISVLSI Zengchao Yan, Jun Lin, Zhongfeng Wang
2019	—	`conf`	A Low-Latency and Low-Complexity Hardware Architecture for CTC Beam Search Decoding. SiPS Siyuan Lu, Jinming Lu, Jun Lin, Zhongfeng Wang, Li Du
2019	Misc	`conf`	A Low-latency Sparse-Winograd Accelerator for Convolutional Neural Networks. ICASSP Haonan Wang, Wenjian Liu, Tianyi Xu, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	A New Clock Phase Calibration Method in High-Speed and High-Resolution DACs. IEEE Trans. Circuits Syst. II Express Briefs Congyi Zhu, Jun Lin, Zhongfeng Wang
2019	—	`conf`	A New Fast-SSC-Flip Decoding of Polar Codes. ICC Yangcan Zhou, Jun Lin, Zhongfeng Wang
2019	C	`conf`	A New Probabilistic Gradient Descent Bit Flipping Decoder for LDPC Codes. ISCAS Hangxuan Cui, Jun Lin, Suwen Song, Zhongfeng Wang
2019	C	`conf`	A Novel Low-Complexity Joint Coding and Decoding Algorithm for NB-LDPC Codes. ISCAS Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	An Efficient Post-Processor for Lowering the Error Floor of LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs Hangxuan Cui, Jun Lin, Zhongfeng Wang
2019	C	`conf`	An Enhanced Offset Min-Sum decoder for 5G LDPC Codes. APCC Hangxuan Cui, Khoa LeTrung, Fakhreddine Ghaffari, David Declercq, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	An Improved Gradient Descent Bit-Flipping Decoder for LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. Hangxuan Cui, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	Analysis and Design of a Large Dither Injection Circuit for Improving Linearity in Pipelined ADCs. IEEE Trans. Very Large Scale Integr. Syst. Congyi Zhu, Renrong Liang, Jun Lin, Zhongfeng Wang, Li Li
2019	J	`jnl`	Background Calibration of Comparator Offsets in SHA-Less Pipelined ADCs. IEEE Trans. Circuits Syst. II Express Briefs Congyi Zhu, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	Design Light-weight 3D Convolutional Networks for Video Recognition Temporal Residual, Fully Separable Block, and Fast Algorithm. CoRR Haonan Wang, Jun Lin, Zhongfeng Wang
2019	—	`conf`	DynExit: A Dynamic Early-Exit Strategy for Deep Residual Networks. SiPS Meiqi Wang, Jianqiao Mo, Jun Lin, Zhongfeng Wang, Li Du
2019	J	`jnl`	E-LSTM: An Efficient Hardware Architecture for Long Short-Term Memory. IEEE J. Emerg. Sel. Topics Circuits Syst. Meiqi Wang, Zhisheng Wang, Jinming Lu, Jun Lin, Zhongfeng Wang
2019	—	`conf`	EAGLE: Exploiting Essential Address in Both Weight and Activation to Accelerate CNN Computing. SiPS Wenjian Liu, Xiayuan Wen, Jun Lin, Zhongfeng Wang, Li Du
2019	J	`jnl`	Efficient T-EMS Based Decoding Algorithms for High-Order LDPC Codes. IEEE Access Jing Tian, Suwen Song, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	FPAP: A Folded Architecture for Energy-Quality Scalable Convolutional Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Yizhi Wang, Jun Lin, Zhongfeng Wang
2019	—	`conf`	Fast-ABC: A Fast Architecture for Bottleneck-Like Based Convolutional Neural Networks. ISVLSI Xiaoru Xie, Fangxuan Sun, Jun Lin, Zhongfeng Wang
2019	—	`conf`	Hardware Implementation of Improved Fast-SSC-Flip Decoder for Polar Codes. ISVLSI Jing Zeng, Yangcan Zhou, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	High-Speed Modular Multipliers for Isogeny-Based Post-Quantum Cryptography. IACR Cryptol. ePrint Arch. Jing Tian, Zhe Liu, Jun Lin, Zhongfeng Wang, Binjing Li
2019	—	`conf`	Hybrid Preconditioned CG Detection with Sequential Update for Massive MIMO Systems. SiPS Jing Zeng, Jun Lin, Zhongfeng Wang, Yun Chen
2019	J	`jnl`	Improved Fast-SSC-Flip Decoding of Polar Codes. IEEE Commun. Lett. Yangcan Zhou, Jun Lin, Zhongfeng Wang
2019	C	`conf`	Methodology for Efficient Reconfigurable Architecture of Generative Neural Network. ISCAS Wendong Mao, Jichen Wang, Jun Lin, Zhongfeng Wang
2019	J	`jnl`	Modified GII-BCH Codes for Low-Complexity and Low-Latency Encoders. IEEE Commun. Lett. Wenjie Li, Jing Tian, Jun Lin, Zhongfeng Wang
2019	—	`conf`	Redundancy-Aided Iterative Reliability-Based Majority-Logic Decoding for NB-LDPC Codes. ASICON Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang
2019	A*	`conf`	TIE: energy-efficient tensor train-based inference engine for deep neural network. ISCA Chunhua Deng, Fangxuan Sun, Xuehai Qian, Jun Lin, Zhongfeng Wang, Bo Yuan
2019	—	`conf`	Training Deep Neural Networks Using Posit Number System. SoCC Jinming Lu, Siyuan Lu, Zhisheng Wang, Chao Fang, Jun Lin, Zhongfeng Wang, Li Du
2019	J	`jnl`	Training Deep Neural Networks Using Posit Number System. CoRR Jinming Lu, Siyuan Lu, Zhisheng Wang, Chao Fang, Jun Lin, Zhongfeng Wang, Li Du
2019	C	`conf`	USCA: A Unified Systolic Convolution Array Architecture for Accelerating Sparse Neural Network. ISCAS Wenjian Liu, Jun Lin, Zhongfeng Wang
2019	—	`conf`	Ultra-Fast Modular Multiplication Implementation for Isogeny-Based Post-Quantum Cryptography. SiPS Jing Tian, Jun Lin, Zhongfeng Wang
2018	J	`jnl`	A 21.66 Gbps Nonbinary LDPC Decoder for High-Speed Communications. IEEE Trans. Circuits Syst. II Express Briefs Jing Tian, Jun Lin, Zhongfeng Wang
2018	—	`conf`	A High-Speed and Low-Complexity Architecture for Softmax Function in Deep Learning. APCCAS Meiqi Wang, Siyuan Lu, Danyang Zhu, Jun Lin, Zhongfeng Wang
2018	—	`conf`	A Low-Complexity Massive MIMO Detection Algorithm Based on Matrix Partition. SiPS Yahui Ji, Zhizhen Wu, Yifei Shen, Jun Lin, Zaichen Zhang, Xiaohu You, Chuan Zhang
2018	C	`conf`	A New Soft-input Hard-output decoding algorithm for Turbo Product Codes. ISCAS Yaqi Wang, Jun Lin, Zhongfeng Wang
2018	—	`conf`	A Novel Compiler for Regular Expression Matching Engine Construction. APCCAS Xin Jin, Jun Lin, Zhongfeng Wang
2018	J	`jnl`	A Stage-Combined Belief Propagation Decoder for Polar Codes. J. Signal Process. Syst. Jin Sha, Jingbo Liu, Jun Lin, Zhongfeng Wang
2018	C	`conf`	An Efficient Convolution Core Architecture for Privacy-Preserving Deep Learning. ISCAS Yizhi Wang, Jun Lin, Zhongfeng Wang
2018	C	`conf`	An Efficient NB-LDPC Decoding Algorithm for Next-Generation Memories. ISCAS Jing Tian, Jun Lin, Zhongfeng Wang
2018	J	`jnl`	An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. Yizhi Wang, Jun Lin, Zhongfeng Wang
2018	J	`jnl`	An Improved Gauss-Seidel Algorithm and Its Efficient Architecture for Massive MIMO Systems. IEEE Trans. Circuits Syst. II Express Briefs Jing Zeng, Jun Lin, Zhongfeng Wang
2018	—	`conf`	An Optimized Architecture For Decomposed Convolutional Neural Networks. ISVLSI Fangxuan Sun, Jun Lin, Zhongfeng Wang
2018	—	`conf`	Analysis of the Dual-Threshold-Based Shrinking Scheme for Efficient NB-LDPC Decoding. APCCAS Jing Tian, Jun Lin, Zhongfeng Wang
2018	Misc	`conf`	Approximate Belief Propagation Decoder for Polar Codes. ICASSP Menghui Xu, Shusen Jing, Jun Lin, Weikang Qian, Zaichen Zhang, Xiaohu You, Chuan Zhang
2018	—	`conf`	Approximate Comparator: Design and Analysis. SiPS Yangcan Zhou, Jun Lin, Jichen Wang, Zhongfeng Wang
2018	—	`conf`	Bandwidth Efficient Architectures for Convolutional Neural Network. SiPS Jichen Wang, Jun Lin, Zhongfeng Wang
2018	Misc	`conf`	Eadnet: Efficient Architecture for Decomposed Convolutional Neural Networks. ICASSP Fangxuan Sun, Jun Lin, Zhongfeng Wang
2018	J	`jnl`	Efficient Hardware Architectures for Deep Convolutional Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. Jichen Wang, Jun Lin, Zhongfeng Wang
2018	Misc	`conf`	Efficient Reconfigurable Hardware Core for Convolutional Neural Networks. ACSSC Haonan Wang, Jun Lin, Yi Xie, Bo Yuan, Zhongfeng Wang
2018	—	`conf`	FPAP: A Folded Architecture for Efficient Computing of Convolutional Neural Networks. ISVLSI Yizhi Wang, Jun Lin, Zhongfeng Wang
2018	—	`conf`	Fast and Low-Complexity Decoding Algorithm and Architecture for Quadruple-Error-Correcting RS codes. APCCAS Zengchao Yan, Wenjie Li, Jun Lin, Zhongfeng Wang
2018	J	`jnl`	Hardware-Oriented Compression of Long Short-Term Memory for Efficient Inference. IEEE Signal Process. Lett. Zhisheng Wang, Jun Lin, Zhongfeng Wang
2018	J	`jnl`	Low Complexity Message Passing Detection Algorithm for Large-Scale MIMO Systems. IEEE Wirel. Commun. Lett. Jing Zeng, Jun Lin, Zhongfeng Wang
2018	J	`jnl`	Parameter-Free ℓ IEEE Commun. Lett. Qiong Wu, Fan Zhang, Hao Wang, Jun Lin, Yang Liu
2018	J	`jnl`	SGAD: Soft-Guided Adaptively-Dropped Neural Network. CoRR Zhisheng Wang, Fangxuan Sun, Jun Lin, Zhongfeng Wang, Bo Yuan
2017	J	`jnl`	Accelerating Recurrent Neural Networks: A Memory-Efficient Approach. IEEE Trans. Very Large Scale Integr. Syst. Zhisheng Wang, Jun Lin, Zhongfeng Wang
2017	J	`jnl`	An access pattern based adaptive mapping function for GPGPU scratchpad memory. IEICE Electron. Express Feng Han, Li Li, Kun Wang, Fan Feng, Hongbing Pan, Jin Sha, Jun Lin
2017	J	`jnl`	Efficient Soft Cancelation Decoder Architectures for Polar Codes. IEEE Trans. Very Large Scale Integr. Syst. Jun Lin, Zhiyuan Yan, Zhongfeng Wang
2017	C	`conf`	Efficient approximate layered LDPC decoder. ISCAS Yangcan Zhou, Jun Lin, Zhongfeng Wang
2017	—	`conf`	Energy efficient SVM classifier using approximate computing. ASICON Yangcan Zhou, Jun Lin, Zhongfeng Wang
2017	—	`conf`	Low-complexity detection algorithms based on matrix partition for massive MIMO. WCSP Haijian Wu, Jun Lin, Chuan Zhang, Zhongfeng Wang
2017	J	`jnl`	Optimized sorting network for successive cancellation list decoding of polar codes. IEICE Electron. Express Kun Wang, Li Li, Feng Han, Fan Feng, Jun Lin, Yuxiang Fu, Jin Sha
2017	J	`jnl`	Parameter-free 𝓵 CoRR Qiong Wu, Fan Zhang, Hao Wang, Jun Lin, Yang Liu
2017	—	`conf`	Reduced complexity message passing detection algorithm in large-scale MIMO systems. WCSP Haochuan Zhu, Jun Lin, Zhongfeng Wang
2016	J	`jnl`	A High Throughput List Decoder Architecture for Polar Codes. IEEE Trans. Very Large Scale Integr. Syst. Jun Lin, Chenrong Xiong, Zhiyuan Yan
2016	J	`jnl`	A Multimode Area-Efficient SCL Polar Decoder. IEEE Trans. Very Large Scale Integr. Syst. Chenrong Xiong, Jun Lin, Zhiyuan Yan
2016	C	`conf`	A high throughput belief propagation decoder architecture for polar codes. ISCAS Jun Lin, Jin Sha, Li Li, Chenrong Xiong, Zhiyuan Yan, Zhongfeng Wang
2016	C	`conf`	Accurate runtime thermal prediction scheme for 3D NoC systems with noisy thermal sensors. ISCAS Yuxiang Fu, Li Li, Hongbing Pan, Kun Wang, Feng Han, Jun Lin
2016	—	`conf`	An Efficient Hardware Architecture for Lossless Data Compression in Data Center. SiPS Zhisheng Wang, Jun Lin, Zhongfeng Wang
2016	J	`jnl`	An ultra-long FFT architecture implemented in a reconfigurable application specified processor. IEICE Electron. Express Feng Han, Li Li, Kun Wang, Fan Feng, Hongbing Pan, Baoning Zhang, Guoqiang He, Jun Lin
2016	J	`jnl`	Design and implementation of high performance matrix inversion based on reconfigurable processor. IEICE Electron. Express Kun Wang, Li Li, Feng Han, Fan Feng, Jun Lin
2016	—	`conf`	Efficient convolution architectures for convolutional neural network. WCSP Jichen Wang, Jun Lin, Zhongfeng Wang
2016	Misc	`conf`	Error performance analysis of the symbol-decision SC polar decoder. ICASSP Chenrong Xiong, Jun Lin, Zhiyuan Yan
2016	—	`conf`	Intra-layer nonuniform quantization of convolutional neural network. WCSP Fangxuan Sun, Jun Lin, Zhongfeng Wang
2016	C	`conf`	Stage-combined belief propagation decoding of polar codes. ISCAS Jin Sha, Jun Lin, Zhongfeng Wang
2016	J	`jnl`	Symbol-Decision Successive Cancellation List Decoder for Polar Codes. IEEE Trans. Signal Process. Chenrong Xiong, Jun Lin, Zhiyuan Yan
2015	J	`jnl`	A High Throughput List Decoder Architecture for Polar Codes. CoRR Jun Lin, Chenrong Xiong, Zhiyuan Yan
2015	Misc	`conf`	A hybrid partial sum computation unit architecture for list decoders of polar codes. ICASSP Jun Lin, Zhiyuan Yan
2015	J	`jnl`	A hybrid partial sum computation unit architecture for list decoders of polar codes. CoRR Jun Lin, Zhiyuan Yan
2015	J	`jnl`	A multi-mode area-efficient SCL polar decoder. CoRR Chenrong Xiong, Jun Lin, Zhiyuan Yan
2015	J	`jnl`	An Efficient List Decoder Architecture for Polar Codes. IEEE Trans. Very Large Scale Integr. Syst. Jun Lin, Zhiyuan Yan
2015	—	`conf`	Efficient approximate ML decoding units for polar list decoders. SiPS Chenrong Xiong, Jun Lin, Zhiyuan Yan
2015	J	`jnl`	Error Performance Analysis of the Symbol-Decision SC Polar Decoder. CoRR Chenrong Xiong, Jun Lin, Zhiyuan Yan
2015	J	`jnl`	Reduced Complexity Belief Propagation Decoders for Polar Codes. CoRR Jun Lin, Chenrong Xiong, Zhiyuan Yan
2015	—	`conf`	Reduced complexity belief propagation decoders for polar codes. SiPS Jun Lin, Chenrong Xiong, Zhiyuan Yan
2015	J	`jnl`	Symbol-Decision Successive Cancellation List Decoder for Polar Codes. CoRR Chenrong Xiong, Jun Lin, Zhiyuan Yan
2014	J	`jnl`	A Reduced Latency List Decoding Algorithm for Polar Codes. CoRR Jun Lin, Chenrong Xiong, Zhiyuan Yan
2014	—	`conf`	A reduced latency list decoding algorithm for polar codes. SiPS Jun Lin, Chenrong Xiong, Zhiyuan Yan
2014	J	`jnl`	An Efficient Fully Parallel Decoder Architecture for Nonbinary LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. Jun Lin, Zhiyuan Yan
2014	J	`jnl`	Efficient Error Control Decoder Architectures for Noncoherent Random Linear Network Coding. J. Signal Process. Syst. Jun Lin, Hongmei Xie, Zhiyuan Yan
2014	C	`conf`	Efficient list decoder architecture for polar codes. ISCAS Jun Lin, Zhiyuan Yan
2014	J	`jnl`	Symbol-Based Successive Cancellation List Decoder for Polar Codes. CoRR Chenrong Xiong, Jun Lin, Zhiyuan Yan
2014	—	`conf`	Symbol-based successive cancellation list decoder for polar codes. SiPS Chenrong Xiong, Jun Lin, Zhiyuan Yan
2013	C	`conf`	A decoding algorithm with reduced complexity for non-binary LDPC codes over large fields. ISCAS Jun Lin, Zhiyuan Yan
2013	J	`jnl`	Efficient Shuffled Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. Jun Lin, Zhiyuan Yan
2013	J	`jnl`	Linearized Polynomial Interpolation and Its Applications. IEEE Trans. Signal Process. Hongmei Xie, Jun Lin, Zhiyuan Yan, Bruce W. Suter
2012	—	`conf`	Efficient Kötter-Kschischang Decoder Architectures for Noncoherent Error Control in Random Linear Network Coding. SiPS Jun Lin, Hongmei Xie, Zhiyuan Yan
2012	C	`conf`	Modified shuffled schedule for nonbinary low-density parity-check codes. ISCAS Jun Lin, Zhiyuan Yan
2012	J	`jnl`	Reduced-Complexity Decoders of Long Reed-Solomon Codes Based on Composite Cyclotomic Fourier Transforms. IEEE Trans. Signal Process. Xuebin Wu, Zhiyuan Yan, Jun Lin
2010	J	`jnl`	An Efficient VLSI Architecture for Nonbinary LDPC Decoders. IEEE Trans. Circuits Syst. II Express Briefs Jun Lin, Jin Sha, Zhongfeng Wang, Li Li
2010	J	`jnl`	Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. Jun Lin, Jin Sha, Zhongfeng Wang, Li Li
2010	J	`jnl`	Flexible LDPC Decoder Design for Multigigabit-per-Second Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Chuan Zhang, Zhongfeng Wang, Jin Sha, Li Li, Jun Lin
2009	—	`conf`	An improved min-sum based column-layered decoding algorithm for LDPC codes. SiPS Jun Lin, Jin Sha, Zhongfeng Wang, Li Li
2009	J	`jnl`	Decoder Design for RS-Based LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs Jin Sha, Jun Lin, Zhongfeng Wang, Li Li, Minglun Gao
2009	J	`jnl`	Efficient Shuffle Network Architecture and Application for WiMAX LDPC Decoders. IEEE Trans. Circuits Syst. II Express Briefs Jun Lin, Zhongfeng Wang, Li Li, Jin Sha, Minglun Gao
2009	C	`conf`	LDPC Decoder Design for IEEE 802.15 Standard. ISCAS Jin Sha, Jun Lin, Li Li, Minglun Gao, Zhongfeng Wang
2009	J	`jnl`	LDPC decoder design for high rate wireless personal area networks. IEEE Trans. Consumer Electron. Jin Sha, Jun Lin, Zhongfeng Wang, Li Li, Minglun Gao
2008	—	`conf`	Low-complexity shift-LDPC decoder for high-speed communication systems. APCCAS Chuan Zhang, Li Li, Jun Lin, Zhongfeng Wang