Jun Han - RankMe

141 papers A* 2A 3B 2C 13Journal 58Unranked 63

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	25.2 A 28nm 0.48mJ/boot Torus FHE Processor for Arbitrary Computation on Encrypted Data. ISSCC Xinglong Yu, Yi Sun, Yifan Zhao, Honglin Kuang, Song Wang, Zhen Yang, Jun Han
2026	J	`jnl`	A Piezoelectric Energy Harvesting Interface With Type Detection and Variable-Duty-Cycle-Based MPPT for Periodic and Shock Vibrations. IEEE J. Solid State Circuits Yiming Feng, Jun Han, Xiaoyang Zeng, Zhiyuan Chen
2026	J	`jnl`	PCMT: Prioritizing Coherence Message Types for NoC Protocol-Level Deadlock Freedom. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yufan Jia, Zhiyuan Zhang, Chao Fu, Li Wan, Jun Han
2025	—	`conf`	A 0.52mJ/Frame 107fps Super-Resolution Processor Exploiting Pseudo-FP6 Sparsity for Mobile Applications. ISSCC Xuyang Duan, Xinhua Shi, Zikang Zhou, Zhiyi Shu, Yitong Rong, Yufan Chen, Zhen Yang, Menghan Li, Jun Han
2025	A*	`conf`	A Memory-Efficient LLM Accelerator with Q-K Correlation Prediction using Cluster-Based Associative Array for Selective KV Accessing. DAC Zikang Zhou, Kaiqi Chen, Xuyang Duan, Jun Han
2025	J	`jnl`	A power-iteration-based beamformer for large-scale antenna arrays. Microelectron. J. Ting Huang, Ziyu Guo, Bo Hu, Xu Cheng, Jun Han, Xiaoyang Zeng
2025	J	`jnl`	ARV-Q: An Adaptive RISC-V Vector Processor for Unified Support of Post-Quantum Standards and Side-Channel Protection on the Edge. IEEE Trans. Circuits Syst. I Regul. Pap. Yifan Zhao, Honglin Kuang, Xinglong Yu, Yi Sun, Ziyi Hao, Jianyi Meng, Jun Han
2025	—	`conf`	An Edge-Cloud Collaborative System for Infrared Video Resolution Enhancement in Sensor-Limited IoT Monitoring. IOT Menghan Li, Sheng Lu, Jinhua Li, Yaqi Chen, Jun Han
2025	C	`conf`	Background Calibration for Mixed Mismatches in TIADC Using Taylor-Volterra-Series-Based Model. ISCAS Song Wang, Xu Cheng, Ziyu Guo, Jun Han
2025	J	`jnl`	BoostTM: Best-effort performance guarantees in best-effort hardware transactional memory for distributed manycore architectures. J. Syst. Archit. Li Wan, Zhiyuan Zhang, Chao Fu, Qiang Li, Jun Han
2025	J	`jnl`	Booth-Assisted Mixed-Precision Reconfigurable Digital Computing-in-Memory Engine With Ternary-Input 1T2R ReRAM for Edge AI. IEEE Trans. Circuits Syst. I Regul. Pap. Ruijun Lin, Lixing Li, Shuyang Lv, Jingwen Jiang, Liang Meng, Zhiwang Guo, Jianguo Yang, Jun Han, Alex Zhou, Xiaoyong Xue, Xiaoyang Zeng
2025	J	`jnl`	Coordinating Binary Trait: Accurate and Lightweight Runtime On-Chip Power Meter Design. IEEE Trans. Very Large Scale Integr. Syst. Qiang Li, Weixi Lyu, Yifan Liu, Jun Tao, Jun Han
2025	J	`jnl`	DARE: An Irregularity-Tolerant Matrix Processing Unit with a Densifying ISA and Filtered Runahead Execution. CoRR Xin Yang, Xin Fan, Zengshi Wang, Jun Han
2025	J	`jnl`	DNA-HHE: Dual-mode Near-network Accelerator for Hybrid Homomorphic Encryption on the Edge. CoRR Yifan Zhao, Xinglong Yu, Yi Sun, Honglin Kuang, Jun Han
2025	J	`jnl`	EF-CIM: An Endurance Friendly CIM Accelerator Using Embedded NVM With Bit-Aware Wear Leveling for Efficient Light-Weight On-Chip Training in Edge Devices. IEEE Trans. Circuits Syst. I Regul. Pap. Zhiwang Guo, Jingwen Jiang, Deyang Chen, Jinbei Fang, Jianguo Yang, Jun Han, Xiaoyong Xue, Xiaoyang Zeng
2025	J	`jnl`	Enhancing Efficiency in Piezoelectric Energy Harvesting: Collaborative-Flip Synchronized Switch Harvesting on Capacitors Rectifier and Multioutput DC-DC Converters Utilizing Shared Capacitors. IEEE J. Solid State Circuits Jing Wang, Yi Yang, Zhen Li, Sijun Du, Xinling Yue, Xun Liu, Jun Han, Xiaoyang Zeng, Zhiyuan Chen
2025	—	`conf`	HCTSR: A Hybrid CNN/Transformer Super-Resolution Processor with Depth-Scalable Non-Overlapping Window Attention. ACM Great Lakes Symposium on VLSI Xinhua Shi, Kaiqi Chen, Xuyang Duan, Jun Han
2025	—	`conf`	Multi-DOF Fusion: A Flexible Fusion Strategy for Reducing Redundancy in CNN Workloads. ACM Great Lakes Symposium on VLSI Yaqi Chen, Zikang Zhou, Siyao Dai, Xuyang Duan, Jun Han
2025	—	`conf`	Sliding-Window Scheduling to Exploit Hybrid-Bonding-Based Accelerators for Fully Homomorphic Encryption. ACM Great Lakes Symposium on VLSI Yi Sun, Xinhua Chen, Xinglong Yu, Wenxuan Zhang, Yifan Zhao, Honglin Kuang, Jun Han
2025	—	`conf`	VLSUMaP: A High-Performance Matrix Processor with Virtually Expanded LSU Boosting HBM Bandwidth Utilization. ACM Great Lakes Symposium on VLSI Xin Yang, Xinjie Kong, Kaixuan Wang, Xin Fan, Zikang Zhou, Zhuoyuan Yang, Zengshi Wang, Jun Han
2024	J	`jnl`	A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using Metastability Detection and Escape Acceleration Technique. IEEE Trans. Circuits Syst. II Express Briefs Jiawei Wang, Zhao Gao, Xu Cheng, Jue Wang, Zhen Li, Jun Han, Xiaoyang Zeng
2024	J	`jnl`	A 28-nm 36 Kb SRAM CIM Engine With 0.173 μm IEEE J. Solid State Circuits Chenyang Zhao, Jinbei Fang, Xiaoli Huang, Deyang Chen, Zhiwang Guo, Jingwen Jiang, Jiawei Wang, Jianguo Yang, Jun Han, Peng Zhou, Xiaoyong Xue, Xiaoyang Zeng
2024	J	`jnl`	A Design Framework for Generating Energy-Efficient Accelerator on FPGA Toward Low-Level Vision. IEEE Trans. Very Large Scale Integr. Syst. Zikang Zhou, Xuyang Duan, Jun Han
2024	—	`conf`	A Hardware-Aware and Content-Adaptive Super Resolution System for Bandwidth-Limited IoT Video Delivery. IoT Xuyang Duan, Zikang Zhou, Wu Qiu, Zhiyi Shu, Zheng Tang, Jun Han
2024	B	`conf`	A Heuristic and Greedy Weight Remapping Scheme with Hardware Optimization for Irregular Sparse Neural Networks Implemented on CIM Accelerator in Edge AI Applications. ASPDAC Lizhou Wu, Chenyang Zhao, Jingbo Wang, Xueru Yu, Shoumian Chen, Chen Li, Jun Han, Xiaoyong Xue, Xiaoyang Zeng
2024	J	`jnl`	A high-throughput and low-storage stereo vision accelerator with dependency-resolving strided aggregation for 8-path semi-global matching. Microelectron. J. Yitong Rong, Xuyang Duan, Jun Han
2024	J	`jnl`	An Energy-Efficient BNN Accelerator With Two-Stage Value Prediction for Sparse-Edge Gesture Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. Yongliang Zhang, Yitong Rong, Xuyang Duan, Zhen Yang, Qiang Li, Ziyu Guo, Xu Cheng, Xiaoyang Zeng, Jun Han
2024	J	`jnl`	Angular Parameter Estimation for Incoherently Distributed Sources With Single RF Chain. IEEE Trans. Signal Process. Ziyu Guo, Tao Yang, Peng Chen, Jun Han, Xiaoyang Zeng, Bo Hu
2024	B	`conf`	Chimera: A co-simulation framework combining with gem5 and FPGA platform for efficient verification. FPL Chao Fu, Zengshi Wang, Jun Han
2024	C	`conf`	Hardware Acceleration of Phase and Gain Control for Analog Beamforming. ISCAS Xinhao Mao, Ziyu Guo, Jun Han, Bo Hu, Xiaoyang Zeng
2024	A	`conf`	LockillerTM: Enhancing Performance Lower Bounds in Best-Effort Hardware Transactional Memory. IPDPS Li Wan, Fu Chao, Qiang Li, Jun Han
2024	—	`conf`	ML-Fusion: Determining Memory Levels for Data Reuse Between DNN Layers. ACM Great Lakes Symposium on VLSI Zikang Zhou, Xuyang Duan, Kaiqi Chen, Yaqi Chen, Jun Han
2024	J	`jnl`	Piezoelectric Energy Harvesting Interface Using Self-Bias-Flip Rectifier and Switched-PEH DC-DC for MPPT. IEEE J. Solid State Circuits Zhen Li, Jing Wang, Man-Kay Law, Sijun Du, Junrui Liang, Xu Cheng, Jun Han, Xiaoyang Zeng, Zhiyuan Chen
2024	A	`conf`	RVCE-FAL: A RISC-V Scalar-Vector Custom Extension for Faster FALCON Digital Signature. DATE Xinglong Yu, Yi Sun, Yifan Zhao, Honglin Kuang, Jun Han
2024	J	`jnl`	SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure. IEEE Trans. Circuits Syst. II Express Briefs Yuanyuan Han, Xu Cheng, Xiaoyong Xue, Jun Han, Jiawei Xu, Xiaoyang Zeng
2023	J	`jnl`	A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Yan Liu, Yan Li, Xu Cheng, Jun Han, Xiaoyang Zeng
2023	—	`conf`	A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter. CICC Zhen Li, Zhiyuan Chen, Man-Kay Law, Sijun Du, Xu Cheng, Xiaoyang Zeng, Jun Han
2023	J	`jnl`	A foreground digital calibration algorithm for time-interleaved ADCs with low computational complexity. Microelectron. J. Song Wang, Xu Cheng, Ziyu Guo, Jun Han
2023	—	`conf`	Coupled Data Prefetch and Cache Partitioning Scheme for CPU-Accelerator System. ASICON Zengshi Wang, Chao Fu, Jun Han
2023	J	`jnl`	DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. Yan Li, Chao Chen, Xu Cheng, Jun Han, Xiaoyang Zeng
2023	J	`jnl`	Dominant-Node Theory and Monitoring-Rescue Method for Eliminating Undesired Operating Points in the Self-Biased Reference Generators. IEEE Trans. Circuits Syst. I Regul. Pap. Baijie Zhang, Jiawei Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
2023	—	`conf`	Enhancing RISC-V Vector Extension for Efficient Application of Post-Quantum Cryptography. ASAP Yifan Zhao, Honglin Kuang, Yi Sun, Zhen Yang, Chen Chen, Jianyi Meng, Jun Han
2023	—	`conf`	General Vector Instruction Extension for GF(2 ASICON Honglin Kuang, Yifan Zhao, Yi Sun, Jun Han
2023	J	`jnl`	SPARK: An automatic Score-Power-Area efficient RISC-V processor microarchitecture SeeKer. Microelectron. J. Qiang Li, Jun Tao, Jun Han
2023	—	`conf`	SVP: Safe and Efficient Speculative Execution Mechanism through Value Prediction. ACM Great Lakes Symposium on VLSI Kaixuan Wang, Xinyu Qin, Zhuoyuan Yang, Weiliang He, Yifan Liu, Jun Han
2023	—	`conf`	UACT: A Unified Energy-efficient Computing Architecture for CNN and TCNN. ASICON Yufan Chen, Xuyang Duan, Jun Han
2023	J	`jnl`	UArch: A Super-Resolution Processor With Heterogeneous Triple-Core Architecture for Workloads of U-Net Networks. IEEE Trans. Biomed. Circuits Syst. Xuyang Duan, Yufan Chen, Menghan Li, Yitong Rong, Ruiqi Xie, Jun Han
2022	C	`conf`	A Cross Regulation Reduced Multi-Output and Multi-VCR Piezoelectric Energy Harvesting System Using Shared Capacitors. ISCAS Jing Wang, Zhiyuan Chen, Junrui Liang, Xu Cheng, Jun Han, Xiaoyang Zeng
2022	J	`jnl`	A High-Performance Domain-Specific Processor With Matrix Extension of RISC-V for Module-LWE Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Yifan Zhao, Ruiqi Xie, Guozhu Xin, Jun Han
2022	—	`conf`	A High-Speed NTT-Based Polynomial Multiplication Accelerator with Vector Extension of RISC-V for Saber Algorithm. APCCAS Honglin Kuang, Yifan Zhao, Jun Han
2022	C	`conf`	A Synthesis Friendly Dynamic Amplifier with Fuzzy-Logic Piecewise-Linear Calibration. ISCAS Jiawei Wang, Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
2022	C	`conf`	An Enhanced Start-up Circuit Eliminating All Trojan States in Self-biased Reference Generators. ISCAS Baijie Zhang, Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
2022	J	`jnl`	LosaTM: A Hardware Transactional Memory Integrated With a Low-Overhead Scenario-Awareness Conflict Manager. IEEE Trans. Parallel Distributed Syst. Chao Fu, Li Wan, Jun Han
2021	J	`jnl`	A 28 nm, 397 μW real-time dynamic gesture recognition chip based on RISC-V processor. Microelectron. J. Yong-Liang Zhang, Qiang Li, Hui Zhang, Wei-Zhen Wang, Jun Han, Xiaoyang Zeng, Xu Cheng
2021	—	`conf`	A CNN Hardware Accelerator Designed for YOLO Algorithm Based on RISC-V SoC. ASICON Xinyu Qin, Xudong Liu, Jun Han
2021	—	`conf`	A Heterogeneous Full-stack AI Platform for Performance Monitoring and Hardware-specific Optimizations. MCSoC Zikang Zhou, Chao Fu, Ruiqi Xie, Jun Han
2021	C	`conf`	A Multi-Layer Parallel Hardware Architecture for Homomorphic Computation in Machine Learning. ISCAS Guozhu Xin, Yifan Zhao, Jun Han
2021	—	`conf`	A Synthesizable 0.0060mm A-SSCC Jue Wang, Zhenyu Yang, Jiawei Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
2021	J	`jnl`	A hardware-efficient dual-source data replication and local broadcast mechanism in distributed shared caches. Microelectron. J. Chao Fu, Yuchao Zhou, Jun Han
2021	J	`jnl`	An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications. IEEE Trans. Circuits Syst. II Express Briefs Keji Zhou, Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Deyang Chen, Yujie Huang, Ming-e Jing, Jun Han, Haidong Tian, Xiankui Xiong, Qi Liu, Xiaoyong Xue, Xiaoyang Zeng
2021	—	`conf`	An Energy-Efficient Image Denoising Accelerator with Depth-wise Separable Convolution and Fused-Layer Architecture. ASICON Xuyang Duan, Ruiqi Xie, Jun Han
2021	J	`jnl`	An energy-efficient crypto-extension design for RISC-V. Microelectron. J. Weizhen Wang, Jun Han, Xu Cheng, Xiaoyang Zeng
2021	J	`jnl`	DyGA: A Hardware-Efficient Accelerator With Traffic-Aware Dynamic Scheduling for Graph Convolutional Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Ruiqi Xie, Jun Yin, Jun Han
2021	J	`jnl`	General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework. IEEE Trans. Circuits Syst. I Regul. Pap. Chiyu Tan, Yan Li, Xu Cheng, Jun Han, Xiaoyang Zeng
2021	J	`jnl`	MC-LSTM: Real-Time 3D Human Action Detection System for Intelligent Healthcare Applications. IEEE Trans. Biomed. Circuits Syst. Jun Yin, Jun Han, Ruiqi Xie, Chenghao Wang, Xuyang Duan, Yitong Rong, Xiaoyang Zeng, Jun Tao
2021	—	`conf`	Mini-HOG: An Area-efficient and Low-power HOG Accelerator with SW/HW co-design for Real-time Pedestrian Detection. ASICON Ruiqi Xie, Jun Han
2021	J	`jnl`	Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. Yuanyuan Han, Tongde Li, Xu Cheng, Liang Wang, Jun Han, Yuanfu Zhao, Xiaoyang Zeng
2021	J	`jnl`	Synthesizable lead-lag quantization technique for digital VCO-based ΔΣ ADC. Microelectron. J. Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
2021	A	`conf`	TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications. DATE Yan Li, Jun Han, Xiaoyang Zeng, Mehdi B. Tahoori
2020	J	`jnl`	A Power Analysis Attack Resistant Multicore Platform With Effective Randomization Techniques. IEEE Trans. Very Large Scale Integr. Syst. Jianwei Yang, Jun Han, Fan Dai, Weizhen Wang, Xiaoyang Zeng
2020	J	`jnl`	A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application. IEEE Trans. Circuits Syst. II Express Briefs Yan Li, Xu Cheng, Chiyu Tan, Jun Han, Yuanfu Zhao, Liang Wang, Tongde Li, Mehdi B. Tahoori, Xiaoyang Zeng
2020	C	`conf`	A Synthesis Friendly VCO-Based Delta-Sigma ADC with Process Variation Tolerance. ISCAS Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
2020	—	`conf`	An Optimization Toolchain Design of Deep Learning Deployment Based on Heterogeneous Computing Platform. WCSP Jun Yin, Jun Han, Xiaodong Zhang
2020	C	`conf`	Design Methodology of Clock Polarity Inversion Technique for Frequency Dividers. ISCAS Xu Cheng, Jue Wang, Jun Han, Xiaoyang Zeng
2020	A*	`conf`	Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit. DAC Yan Li, Xiaoyoung Zeng, Zhengqi Gao, Liyu Lin, Jun Tao, Jun Han, Xu Cheng, Mehdi B. Tahoori, Xiaoyang Zeng
2020	J	`jnl`	Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications. IEEE Trans. Very Large Scale Integr. Syst. Yuanyuan Han, Xu Cheng, Jun Han, Xiaoyang Zeng
2020	J	`jnl`	VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. Guozhu Xin, Jun Han, Tianyu Yin, Yuchao Zhou, Jianwei Yang, Xu Cheng, Xiaoyang Zeng
2019	—	`conf`	A Hardware-efficient Accelerator for Encoding Stage of Text-to-speech Synthesis. ASICON Riyong Zheng, Chenghao Wang, Jun Han, Xiaoyang Zeng
2019	J	`jnl`	A Real-Time and Hardware-Efficient Processor for Skeleton-Based Action Recognition With Lightweight Convolutional Neural Network. IEEE Trans. Circuits Syst. II Express Briefs Bingyi Zhang, Jun Han, Zhize Huang, Jianwei Yang, Xiaoyang Zeng
2019	—	`conf`	A Skeleton-based Action Recognition System for Medical Condition Detection. BioCAS Jun Yin, Jun Han, Chenghao Wang, Bingyi Zhang, Xiaoyang Zeng
2018	J	`jnl`	Countering power analysis attacks by exploiting characteristics of multicore processors. IEICE Electron. Express Jianwei Yang, Fan Dai, Jielin Wang, Jianmin Zeng, Zhang Zhang, Jun Han, Xiaoyang Zeng
2018	—	`conf`	MiniTracker: A Lightweight CNN-based System for Visual Object Tracking on Embedded Device. DSP Bingyi Zhang, Xin Li, Jun Han, Xiaoyang Zeng
2018	—	`conf`	The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization. ISOCC Yujie Huang, Yujie Cai, Ming-e Jing, Jun Han, Yibo Fan, Xiaoyang Zeng
2017	—	`conf`	A configurable nonlinear operation unit for neural network accelerator. ASICON Yujie Cai, Xin Li, Jun Han, Xiaoyang Zeng
2017	—	`conf`	A high utilization FPGA-based accelerator for variable-scale convolutional neural network. ASICON Xin Li, Yujie Cai, Jun Han, Xiaoyang Zeng
2017	J	`jnl`	A multi-core-based heterogeneous parallel turbo decoder. IEICE Electron. Express Jianmin Zeng, Chubin Wu, Zhang Zhang, Xin Cheng, Guangjun Xie, Jun Han, Xiaoyang Zeng, Zhiyi Yu
2017	—	`conf`	FPGA-based efficient implementation of SURF algorithm. ASICON Ying Zhang, Yujie Huang, Jun Han, Xiaoyang Zeng
2017	—	`conf`	Fp ASICON Yalong Pang, Ying Zhang, Jun Han, Xiaoyang Zeng
2017	—	`conf`	Instruction set extension and hardware acceleration for SVM application toward a vector processor. ISOCC Yalong Pang, Jun Han, Jianmin Zeng, Yujie Huang, Xiaoyang Zeng
2017	—	`conf`	Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design. ASICON Jianwei Yang, Weizhen Wang, Zhicheng Xie, Jun Han, Zhiyi Yu, Xiaoyang Zeng
2016	—	`conf`	A low-cost and energy-efficient EEG processor for continuous seizure detection using wavelet transform and AdaBoost. BioCAS Shan Huang, Jun Han, Xin Li, Zongxian Yang, Xiaoyang Zeng
2016	J	`jnl`	An Area-Efficient Error-Resilient Ultralow-Power Subthreshold ECG Processor. IEEE Trans. Circuits Syst. II Express Briefs Jun Han, Yicheng Zhang, Shan Huang, Mengyuan Chen, Xiaoyang Zeng
2016	—	`conf`	Cryptographie coprocessor design for IoT sensor nodes. ISOCC Weizhen Wang, Jun Han, Zhicheng Xie, Shan Huang, Xiaoyang Zeng
2015	J	`jnl`	A 1.5-D Multi-Channel EEG Compression Algorithm Based on NLSPIHT. IEEE Signal Process. Lett. Gaowei Xu, Jun Han, Yao Zou, Xiaoyang Zeng
2015	J	`jnl`	A 65 nm Cryptographic Processor for High Speed Pairing Computation. IEEE Trans. Very Large Scale Integr. Syst. Jun Han, Yang Li, Zhiyi Yu, Xiaoyang Zeng
2015	J	`jnl`	A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation. IEEE Trans. Circuits Syst. I Regul. Pap. Jun Han, Renfeng Dou, Lingyun Zeng, Shuai Wang, Zhiyi Yu, Xiaoyang Zeng
2015	—	`conf`	A SIMD multiplier-accumulator design for pairing cryptography. ASICON Weizhen Wang, Jun Han, Jielin Wang, Xiaoyang Zeng
2015	—	`conf`	A configurable SoC design for information security. ASICON Sizhong Xuan, Jun Han, Zhiyi Yu, Yi Ren, Xiaoyang Zeng
2015	—	`conf`	A lifting-based 2-D discrete wavelet transform architecture for data compression of bio-potential signals. ASICON Yi Ren, Jun Han, Zhiyi Yu, Sizhong Xuan, Xiaoyang Zeng
2015	—	`conf`	A low-cost SoC implementation of AES algorithm for bio-signals. ASICON Zhicheng Xie, Jun Han, Jianwei Yang, Lijun Zhou, Xiaoyang Zeng
2015	J	`jnl`	An Energy-Efficient Design for ECG Recording and R-Peak Detection Based on Wavelet Transform. IEEE Trans. Circuits Syst. II Express Briefs Yao Zou, Jun Han, Sizhong Xuan, Shan Huang, Xinqian Weng, Dabin Fang, Xiaoyang Zeng
2015	J	`jnl`	Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process. IEEE Trans. Very Large Scale Integr. Syst. Xiaoyang Zeng, Yi Li, Yuejun Zhang, Shujie Tan, Jun Han, Xingxing Zhang, Zhang Zhang, Xu Cheng, Zhiyi Yu
2015	—	`conf`	Exploration for energy-efficient ECC decoder of WBAN. ASICON Tianchan Guan, Jun Han, Xiaoyang Zeng
2015	—	`conf`	Motion artifact removal based on ICA for ambulatory ECG monitoring. ASICON Shudong Tian, Jun Han, Jianwei Yang, Lijun Zhou, Xiaoyang Zeng
2015	—	`conf`	Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design. ASICON Jielin Wang, Weizhen Wang, Jianwei Yang, Zhiyi Yu, Jun Han, Xiaoyang Zeng
2014	J	`jnl`	A 16-Core Processor With Shared-Memory and Message-Passing Communications. IEEE Trans. Circuits Syst. I Regul. Pap. Zhiyi Yu, Ruijin Xiao, Kaidi You, Heng Quan, Peng Ou, Zheng Yu, Maofei He, Jiajie Zhang, Yan Ying, Haofan Yang, Jun Han, Xu Cheng, Zhang Zhang, Ming-e Jing, Xiaoyang Zeng
2014	J	`jnl`	An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture. IEEE Trans. Very Large Scale Integr. Syst. Renfeng Dou, Jun Han, Yifan Bo, Zhiyi Yu, Xiaoyang Zeng
2014	J	`jnl`	An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing. IEICE Electron. Express Yi Li, Liang Wen, Yuejun Zhang, Xu Cheng, Jun Han, Zhiyi Yu, Xiaoyang Zeng
2014	—	`conf`	An error-resilient wavelet-based ECG processor under voltage overscaling. BioCAS Mengyuan Chen, Jun Han, Yicheng Zhang, Yao Zou, Yi Li, Xiaoyang Zeng
2013	—	`conf`	A 920MHz quad-core cryptography processor accelerating parallel task processing of public-key algorithms. CICC Shuai Wang, Jun Han, Yang Li, Yifan Bo, Xiaoyang Zeng
2013	—	`conf`	A hardware-efficient variable-length FFT processor for low-power applications. APSIPA Yifan Bo, Renfeng Dou, Jun Han, Xiaoyang Zeng
2013	—	`conf`	A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs. BioCAS Yi Li, Xu Cheng, Yicheng Zhang, Weijing Shi, Jun Han, Xiaoyang Zeng
2013	J	`jnl`	An Ultra-Low Power QRS Complex Detection Algorithm Based on Down-Sampling Wavelet Transform. IEEE Signal Process. Lett. Yao Zou, Jun Han, Xinqian Weng, Xiaoyang Zeng
2013	—	`conf`	An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP. ASICON Weijing Shi, Yi Li, Jun Han, Xu Cheng, Xiaoyang Zeng
2013	—	`conf`	An ultra low-power and area-efficient baseband processor for WBAN transmitter. APSIPA Mengyuan Chen, Jun Han, Dabin Fang, Yao Zou, Xiaoyang Zeng
2013	J	`jnl`	Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Pengjun Wang, Yuejun Zhang, Jun Han, Zhiyi Yu, Yibo Fan, Zhang Zhang
2013	—	`conf`	Design of a high throughput configurable variable-length FFT processor based on switch network architecture. ASICON Renfeng Dou, Yifan Bo, Jun Han, Xiaoyang Zeng
2013	—	`conf`	Highly flexible WBAN transmit-receive system based on USRP. ASICON Tianchan Guan, Jun Han, Xiaoyang Zeng
2013	—	`conf`	Low power design for FIR filter. ASICON Gaowei Xu, Yao Zou, Jun Han, Xiaoyang Zeng
2013	J	`jnl`	Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform. IEEE Trans. Very Large Scale Integr. Syst. Jun Han, Shuai Wang, Wei Huang, Zhiyi Yu, Xiaoyang Zeng
2013	—	`conf`	Robustness Analysis of Mesh-Based Network-on-Chip Architecture under Flooding-Based Denial of Service Attacks. NAS Dabin Fang, Huikai Li, Jun Han, Xiaoyang Zeng
2012	J	`jnl`	A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS. IEICE Electron. Express Jun Han, Xingxing Zhang, Yi Li, Baoyu Xiong, Yuejun Zhang, Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng
2012	J	`jnl`	A High Speed Reconfigurable Face Detection Architecture Based on AdaBoost Cascade Algorithm. IEICE Trans. Inf. Syst. Weina Zhou, Lin Dai, Yao Zou, Xiaoyang Zeng, Jun Han
2012	—	`conf`	A low power ASIP for precision configurable FFT processing. APSIPA Yifan Bo, Jun Han, Yao Zou, Xiaoyang Zeng
2012	J	`jnl`	Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm. IEICE Trans. Electron. Yuli Zhang, Jun Han, Xinqian Weng, Zhongzhu He, Xiaoyang Zeng
2011	—	`conf`	A NoC-based multi-core architecture for IEEE 802.11i CCMP. ASICON Yang Li, Jun Han, Shuai Wang, Junbao Liu, Xiaoyang Zeng
2011	—	`conf`	A control scheme for a 65nm 32×32b 4-read 2-write register file. ASICON Jun Han, Xingxing Zhang, Baoyu Xiong, Zhiyi Yu, Xiaoyang Zeng
2011	—	`conf`	A security processor based on MIPS 4KE architecture. ASICON Shuai Wang, Yang Li, Junbao Liu, Jun Han, Xiaoyang Zeng
2011	—	`conf`	Analysis of adaptive support-weight based stereo matching for hardware realization. ASICON Junbao Liu, Shuai Wang, Yang Li, Jun Han, Xiaoyang Zeng
2011	—	`conf`	Design of a single-ended cell based 65nm 32×32b 4R2W register file. ASICON Baoyu Xiong, Xingxing Zhang, Jun Han, Zhiyi Yu, Xiaoyang Zeng
2010	—	`conf`	Optimized digital automatic gain control for DVB-S2 system. WTS Yulong Zhang, Jialin Cao, Chuan Wu, Jun Han, Xiaoyang Zeng
2010	—	`conf`	Robust and reliable frame synchronization method for DVB-S2 system. WTS Yulong Zhang, Xubin Chen, Wenhua Fan, Jun Han, Xiaoyang Zeng
2009	—	`conf`	A multi-task-oriented security processing architecture with powerful extensibility. ASP-DAC Dan Cao, Jun Han, Xiaoyang Zeng, Shi-ting Lu
2008	C	`conf`	A full-custom design of AES SubByte module with signal independent power consumption. ISCAS Liang Li, Jun Han, Xiaoyang Zeng, Jia Zhao
2008	—	`conf`	A low-cost cryptographic processor for security embedded system. ASP-DAC Ronghua Lu, Jun Han, Xiaoyang Zeng, Qing Li, Lang Mai, Jia Zhao
2008	C	`conf`	Optimal frame synchronization for DVB-S2. ISCAS Li Qing, Xiaoyang Zeng, Chuan Wu, Yulong Zhang, Yunsong Deng, Jun Han
2008	C	`conf`	Tracking loop for IR-UWB communications in IEEE 802.15 multi-path channels. ISCAS Daxian Yun, Yanjie Peng, Jun Han, Xiaoyang Zeng
2007	C	`conf`	A Low-cost and High-performance SoC Design for OMA DRM2 Applications. ISCAS Yehua Gu, Xiaoyang Zeng, Jun Han, Jia Zhao
2007	C	`conf`	An Energy-Proportion Synchronization Method for IR-UWB Communications. ISCAS Jing Wang, Lang Mai, Yanjie Peng, Jun Han, Xiaoyang Zeng
2007	—	`conf`	Two-dimensional Parity-based Concurrent Error Detection Method for AES Algorithm against Differential Fault Attack and its VLSI Implementation. SiPS Jia Zhao, Jun Han, Xiaoyang Zeng, Yunsong Deng
2006	—	`conf`	A high-performance platform-based SoC for information security. ASP-DAC Min Wu, Xiaoyang Zeng, Jun Han, Yongyi Wu, Yibo Fan