Jun Furuta

34 papers C 5Journal 15Unranked 14
YearRankTypeTitle / Venue / Authors
2025 J jnl
920-MHz Fully-Integrated LNA Operated in Moderate-Inversion Region.
IEICE Trans. Electron.
Nobuyuki Itoh, Kazuya Miyazaki, Mitsuki Miyake, Kiyotaka Komoku, Jun Furuta
2025 C conf
Comparative Analysis of TID Effects in a 65 nm FD-SOI Process Under Gamma-Ray and Alpha-Ray Irradiation.
IOLTS
Hikaru Nakamoto, Taiki Ozawa, Ryuichi Nakajima, Haruto Sugisaki, Keita Yoshida, Jun Furuta, Kazutoshi Kobayashi
2025 J jnl
Radiation-Hardened Flip-Flops in a 65 nm Bulk Process for Terrestrial Applications Coping with Radiation Hardness and Performance Overheads.
IEICE Trans. Electron.
Shotaro Sugitani, Ryuichi Nakajima, Keita Yoshida, Jun Furuta, Kazutoshi Kobayashi
2024 — conf
A Partially-redundant Flip-flip Suitable for Mitigating Single Event Upsets in a FD-SOI Process with Low Performance Overhead.
IRPS
Jun Furuta, Shotaro Sugitani, Ryuichi Nakajima, Kazutoshi Kobayashi
2024 — conf
An Approach to Neutron-Induced SER Evaluation Using a Clinical 290 MeV/ u Carbon Beam and Particle Transport Simulations.
IRPS
Ryuichi Nakajima, Shotaro Sugitani, Haruto Sugisaki, Takafumi Ito, Jun Furuta, Kazutoshi Kobayashi, Makoto Sakai
2024 J jnl
Frequency dependence of soft error rates induced by alpha-particle and heavy ion.
IEICE Electron. Express
Haruto Sugisaki, Ryuichi Nakajima, Shotaro Sugitani, Jun Furuta, Kazutoshi Kobayashi
2024 J jnl
Measuring SET Pulse Widths in pMOSFETs and nMOSFETs Separately by Heavy Ion and Neutron Irradiation.
IEICE Trans. Electron.
Jun Furuta, Shotaro Sugitani, Ryuichi Nakajima, Takafumi Ito, Kazutoshi Kobayashi
2024 J jnl
Soft-Error Tolerance by Guard-Gate Structures on Flip-Flops in 22 and 65 nm FD-SOI Technologies.
IEICE Trans. Electron.
Ryuichi Nakajima, Takafumi Ito, Shotaro Sugitani, Tomoya Kii, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi, Mathieu Louvat, Francois Jacquet, Jean-Christophe Eloy, Olivier Montfort, Lionel Jure, Vincent Huard
2023 — conf
Frequency Dependency of Soft Error Rates Based on Dynamic Soft Error Measurements.
ICICDT
Haruto Sugisaki, Ryuichi Nakajima, Shotaro Sugitani, Jun Furuta, Kazutoshi Kobayashi
2023 — conf
Radiation Hardened Flip-Flops with low Area, Delay and Power Overheads in a 65 nm bulk process.
IRPS
Shotaro Sugitani, Ryuichi Nakajima, Keita Yoshida, Jun Furuta, Kazutoshi Kobayashi
2023 C conf
Radiation Hardness Evaluations of a Stacked Flip Flop in a 22 nm FD-SOI Process by Heavy-Ion Irradiation.
IOLTS
Shotaro Sugitani, Ryuichi Nakajima, Takafumi Ito, Jun Furuta, Kazutoshi Kobayashi, Mathieu Louvat, Francois Jacquet, Jean-Christophe Eloy, Olivier Montfort, Lionel Jure, Vincent Huard
2023 — conf
SEU Sensitivity of PMOS and NMOS Transistors in a 65 nm Bulk Process by α-Particle Irradiation.
ICICDT
Keita Yoshida, Ryuichi Nakajima, Shotaro Sugitani, Takafumi Ito, Jun Furuta, Kazutoshi Kobayashi
2023 — conf
Ultra Long-term Measurement Results of BTI-induced Aging Degradation on 7-nm Ring Oscillators.
IRPS
Kazutoshi Kobayashi, Tomoharu Kishita, Hiroki Nakano, Jun Furuta, Mitsuhiko Igarashi, Shigetaka Kumashiro, Michitarou Yabuuchi, Hironori Sakamoto
2022 C conf
Radiation Hardened Flip-Flops Minimizing Area, Power, and Delay Overheads with 1/100 Lower α-SER in a 130 nm Bulk Process.
IOLTS
Ryuichi Nakajima, Kazuya Ioki, Jun Furuta, Kazutoshi Kobayashi
2021 J jnl
An E-mode p-GaN HEMT monolithically-integrated three-level gate driver operating with a single voltage supply.
IEICE Electron. Express
Junichiro Nagao, Urmimala Chatterjee, Xiangdong Li, Jun Furuta, Stefaan Decoutere, Kazutoshi Kobayashi
2020 J jnl
Evaluation of Heavy-Ion-Induced Single Event Upset Cross Sections of a 65-nm Thin BOX FD-SOI Flip-Flops Composed of Stacked Inverters.
IEICE Trans. Electron.
Kentaro Kojima, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi
2019 — conf
An Accurate Device-Level Simulation Method to Estimate Cross Sections of Single Event Upsets by Silicon Thickness in Raised Layer.
IRPS
Kentaro Kojima, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi
2019 J jnl
Characterizing SRAM and FF soft error rates with measurement and simulation.
Integr.
Masanori Hashimoto, Kazutoshi Kobayashi, Jun Furuta, Shin-ichiro Abe, Yukinobu Watanabe
2019 C conf
Comparison of Radiation Hardness of Stacked Transmission-Gate Flip Flop and Stacked Tristate-Inverter Flip Flop in a 65 nm Thin BOX FDSOI Process.
IOLTS
Mitsunori Ebara, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi
2019 — conf
Impact of Combinational Logic Delay for Single Event Upset on Flip Flops in a 65 nm FDSOI Process.
IRPS
Jun Furuta, Yuto Tsukita, Kodai Yamada, Mitsunori Ebara, Kentaro Kojima, Kazutoshi Kobayashi
2019 J jnl
Monolithic integration of gate driver and p-GaN power HEMT for MHz-switching implemented by e-mode GaN-on-SOI process.
IEICE Electron. Express
Yuki Yamashita, Steve Stoffels, Niels Posthuma, Karen Geens, Xiangdong Li, Jun Furuta, Stefaan Decoutere, Kazutoshi Kobayashi
2019 — conf
Soft-Error Tolerance Depending on Supply Voltage by Heavy Ions on Radiation-Hardened Flip Flops in a 65 nm Bulk Process.
ASICON
Yuto Tsukita, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi
2019 — conf
Temperature Dependence of Bias Temperature Instability (BTI) in Long-term Measurement by BTI-sensitive and -insensitive Ring Oscillators Removing Environmental Fluctuation.
ASICON
Takuya Asuke, Ryo Kishida, Jun Furuta, Kazutoshi Kobayashi
2019 C conf
Total Ionizing Dose Effects by alpha irradiation on circuit performance and SEU tolerance in thin BOX FDSOI process.
IOLTS
Takashi Yoshida, Kazutoshi Kobayashi, Jun Furuta
2018 J jnl
A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process.
IEICE Trans. Electron.
Haruki Maruoka, Masashi Hifumi, Jun Furuta, Kazutoshi Kobayashi
2018 — conf
Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process.
IRPS
Kodai Yamada, Haruki Maruoka, Jun Furuta, Kazutoshi Kobayashi
2017 — conf
Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS.
ICICDT
Takuya Komawaki, Michitarou Yabuuchi, Ryo Kishida, Jun Furuta, Takashi Matsumoto, Kazutoshi Kobayashi
2017 J jnl
Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takuya Komawaki, Michitarou Yabuuchi, Ryo Kishida, Jun Furuta, Takashi Matsumoto, Kazutoshi Kobayashi
2015 J jnl
Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets.
IEICE Trans. Electron.
Jun Furuta, Kazutoshi Kobayashi, Hidetoshi Onodera
2013 J jnl
A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect.
IEICE Trans. Electron.
Kuiyuan Zhang, Jun Furuta, Ryosuke Yamamoto, Kazutoshi Kobayashi, Hidetoshi Onodera
2011 — conf
A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles.
ASP-DAC
Jun Furuta, Chikara Hamanaka, Kazutoshi Kobayashi, Hidetoshi Onodera
2011 — conf
Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm.
A-SSCC
Jun Furuta, Ryosuke Yamamoto, Kazutoshi Kobayashi, Hidetoshi Onodera
2011 J jnl
Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chikara Hamanaka, Ryosuke Yamamoto, Jun Furuta, Kanto Kubota, Kazutoshi Kobayashi, Hidetoshi Onodera
2010 J jnl
An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity.
IEICE Trans. Electron.
Jun Furuta, Kazutoshi Kobayashi, Hidetoshi Onodera