Jun Cao

32 papers Journal 14Unranked 18
YearRankTypeTitle / Venue / Authors
2026 — conf
A 0.008mm
ISSCC
Ahmed Elkholy, Yousr Ismail, Zhi Chao Huang, Adesh Garg, Ali Nazemi, Jun Cao, Afshin Momtaz
2025 J jnl
An 800GbE PAM-4 PHY Transceiver for 42 dB Copper and Direct-Drive Optical Applications in 7 nm.
IEEE Solid State Circuits Lett.
Chang Liu, Burak Catli, Yong Liu, Anand Vasani, Guansheng Li, Kun Chuai, Lakshmi P. Rao, Yang Liu, Xin Meng, Jiawen Zhang, Tim He, Batu Dayanik, Vadim Milirud, Meisam Honarvar Nazari, Hyo Gyuem Rhew, Derui Kong, Arvindh Iyer, Nan Wang, Alireza Nilchi, Aminghasem Safarian, Ray Wang, Hyung-Joon Jeon, Xiaochen Yang, Boyu Hu, Jerry Han, Adesh Garg, Kumar Thasari, Heng Zhang, Namik Kocaman, Ali Nazemi, Delong Cui, Afshin Momtaz, Jun Cao
2025 — conf
An 800GbE PAM-4 PHY Transceiver that Supports 42dB Copper and Direct-Drive Optical Applications in 7nm.
CICC
Chang Liu, Burak Çatli, Yong Liu, Anand Vasani, Guansheng Li, Kun Chuai, Lakshmi P. Rao, Yang Liu, Xin Meng, Jiawen Zhang, Tim He, Batu Dayanik, Vadim Milirud, Meisam Honarvar Nazari, Hyo Gyuem Rhew, Derui Kong, Arvindh Iyer, Nan Wang, Alireza Nilchi, Aminghasem Safarian, Ray Wang, Hyung-Joon Jeon, Alex Yang, Boyu Hu, Jerry Han, Adesh Garg, Kumar Thasari, Heng Zhang, Namik Kocaman, Ali Nazemi, Delong Cui, Afshin Momtaz, Jun Cao
2024 — conf
18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS.
ISSCC
Guansheng Li, Adesh Garg, Tim He, Ullas Singh, Jiawen Zhang, Lakshmi P. Rao, Chang Liu, Meisam Honarvar Nazari, Yang Liu, Yong Liu, Heng Zhang, Tamer A. Ali, Hyo Gyuem Rhew, Jiayoon Ru, Delong Cui, Ali Nazemi, Bo Zhang, Afshin Momtaz, Jun Cao
2024 J jnl
A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology.
IEEE J. Solid State Circuits
Bo Zhang, Anand Vasani, Ashutosh Sinha, Alireza Nilchi, Haitao Tong, Lakshmi P. Rao, Karapet Khanoyan, Hamid Hatamkhani, Xiaochen Yang, Xin Meng, Alexander Wong, Jun Kim, Ping Jing, Yehui Sun, Ali Nazemi, Dean Liu, Anthony Brewster, Jun Cao, Afshin Momtaz
2023 — conf
A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in 7nm FinFET Technology.
ISSCC
Bo Zhang, Anand Vasani, Ashutosh Sinha, Alireza Nilchi, Haitao Tong, Lakshmi P. Rao, Karapet Khanoyan, Hamid Hatamkhani, Xiaochen Yang, Xin Meng, Alexander Wong, Jun Kim, Ping Jing, Yehui Sun, Ali Nazemi, Dean Liu, Anthony Brewster, Jun Cao, Afshin Momtaz
2017 — conf
29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS.
ISSCC
Jun Cao, Delong Cui, Ali Nazemi, Tim He, Guansheng Li, Burak Çatli, Mehdi Khanpour, Kangmin Hu, Tamer A. Ali, Heng Zhang, Hairong Yu, Ben Rhew, Shiwei Sheng, Yonghyun Shim, Bo Zhang, Afshin Momtaz
2016 — conf
3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOS.
ISSCC
Delong Cui, Heng Zhang, Nick Huang, Ali Nazemi, Burak Çatli, Hyo Gyuem Rhew, Bo Zhang, Afshin Momtaz, Jun Cao
2016 — conf
A 125 mW 8.5-11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOS.
VLSI Circuits
Bharath Raghavan, Aida Varzaghani, Lakshmi P. Rao, Henry Park, Xiaochen Yang, Zhi Huang, Yu Chen, Rama Kattamuri, Chunhui Wu, Bo Zhang, Jun Cao, Afshin Momtaz, Namik Kocaman
2015 — conf
3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS.
ISSCC
Ali Nazemi, Kangmin Hu, Burak Çatli, Delong Cui, Ullas Singh, Tim He, Zhi Chao Huang, Bo Zhang, Afshin Momtaz, Jun Cao
2015 J jnl
A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5-11.5 Gb/s Serial Links.
IEEE J. Solid State Circuits
Bo Zhang, Ali Nazemi, Adesh Garg, Namik Kocaman, Mahmoud Reza Ahmadi, Mehdi Khanpour, Heng Zhang, Jun Cao, Afshin Momtaz
2015 J jnl
An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS.
IEEE J. Solid State Circuits
Sui Huang, Jun Cao, Michael M. Green
2015 — conf
Standing wave based clock distribution technique with application to a 10 × 11 Gbps transceiver in 28 nm CMOS.
A-SSCC
Guansheng Li, Wooram Lee, Delong Cui, Bo Zhang, Afshin Momtaz, Jun Cao
2014 — conf
2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS.
ISSCC
Ullas Singh, Adesh Garg, Bharath Raghavan, Nick Huang, Heng Zhang, Zhi Huang, Afshin Momtaz, Jun Cao
2014 — conf
8.8 An 8.2-to-10.3Gb/s full-rate linear reference-less CDR without frequency detector in 0.18μm CMOS.
ISSCC
Sui Huang, Jun Cao, Michael M. Green
2014 J jnl
A 780 mW 4 × 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS.
IEEE J. Solid State Circuits
Ullas Singh, Adesh Garg, Bharath Raghavan, Nick Huang, Heng Zhang, Zhi Chao Huang, Afshin Momtaz, Jun Cao
2014 — conf
A quad-channel 112-128 Gb/s coherent transmitter in 40 nm CMOS.
VLSIC
Adesh Garg, Ullas Singh, Nick Huang, Wayne Wong, Bin Liu, Zhi Chao Huang, Afshin Momtaz, Jun Cao
2013 — conf
A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOS.
ISSCC
Bo Zhang, Ali Nazemi, Adesh Garg, Namik Kocaman, Mahmoud Reza Ahmadi, Mehdi Khanpour, Heng Zhang, Jun Cao, Afshin Momtaz
2013 J jnl
A Sub-2 W 39.8-44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS.
IEEE J. Solid State Circuits
Bharath Raghavan, Delong Cui, Ullas Singh, Hassan Maarefi, Deyi Pi, Anand Vasani, Zhi Chao Huang, Burak Çatli, Afshin Momtaz, Jun Cao
2013 — conf
A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS.
ISSCC
Bharath Raghavan, Delong Cui, Ullas Singh, Hassan Maarefi, Dave Pi, Anand Vasani, Zhi Chao Huang, Afshin Momtaz, Jun Cao
2013 J jnl
Non-idealities in linear CDR phase detectors.
Int. J. Circuit Theory Appl.
Jun Cao, Sui Huang, Michael M. Green
2012 J jnl
A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission.
IEEE J. Solid State Circuits
Delong Cui, Bharath Raghavan, Ullas Singh, Anand Vasani, Zhi Chao Huang, Deyi Pi, Mehdi Khanpour, Ali Nazemi, Hassan Maarefi, Wei Zhang, Tamer A. Ali, Nick Huang, Bo Zhang, Afshin Momtaz, Jun Cao
2012 — conf
A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission.
ISSCC
Delong Cui, Bharath Raghavan, Ullas Singh, Anand Vasani, Zhi Chao Huang, Deyi Pi, Mehdi Khanpour, Ali Nazemi, Hassan Maarefi, Tamer A. Ali, Nick Huang, Wei Zhang, Bo Zhang, Afshin Momtaz, Jun Cao
2011 J jnl
11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications.
IEEE J. Solid State Circuits
Namik Kocaman, Adesh Garg, Bharath Raghavan, Delong Cui, Anand Vasani, Keith Tang, Deyi Pi, Haitao Tong, Siavash Fallahi, Wei Zhang, Ullas Singh, Jun Cao, Bo Zhang, Afshin Momtaz
2011 — conf
11.3Gb/s CMOS SONET-compliant transceiver for both RZ and NRZ applications.
ISSCC
Namik Kocaman, Adesh Garg, Bharath Raghavan, Delong Cui, Anand Vasani, Keith Tang, Deyi Pi, Haitao Tong, Siavash Fallahi, Wei Zhang, Ullas Singh, Jun Cao, Bo Zhang, Afshin Momtaz
2011 — conf
Non-idealities in linear CDR phase detectors.
ECCTD
Jun Cao, Sui Huang, Michael M. Green
2010 J jnl
A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber.
IEEE J. Solid State Circuits
Jun Cao, Bo Zhang, Ullas Singh, Delong Cui, Anand Vasani, Adesh Garg, Wei Zhang, Namik Kocaman, Deyi Pi, Bharath Raghavan, Hui Pan, Ichiro Fujimori, Afshin Momtaz
2009 — conf
21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber.
ISSCC
Jun Cao, Bo Zhang, Ullas Singh, Delong Cui, Anand Vasani, Adesh Garg, Wei Zhang, Namik Kocaman, Deyi Pi, Bharath Raghavan, Hui Pan, Ichiro Fujimori, Afshin Momtaz
2007 J jnl
A Fully Integrated 10-Gb/s Receiver With Adaptive Optical Dispersion Equalizer in 0.13-µm CMOS.
IEEE J. Solid State Circuits
Afshin Momtaz, David Chung, Namik Kocaman, Jun Cao, Mario Caresosa, Bo Zhang, Ichiro Fujimori
2002 J jnl
OC-192 transmitter and receiver in standard 0.18-μm CMOS.
IEEE J. Solid State Circuits
Jun Cao, Michael M. Green, Afshin Momtaz, Kambiz Vakilian, David Chung, Keh-Chee Jen, Mario Caresosa, Xin Wang, Wee-Guan Tan, Yijun Cai, Ichiro Fujimori, Armond Hairapetian
2001 J jnl
A fully integrated SONET OC-48 transceiver in standard CMOS.
IEEE J. Solid State Circuits
Afshin Momtaz, Jun Cao, Mario Caresosa, Armond Hairapetian, David Chung, Kambiz Vakilian, Michael M. Green, Wee-Guan Tan, Keh-Chee Jen, Ichiro Fujimori, Yijun Cai
2000 J jnl
A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8× oversampling ratio.
IEEE J. Solid State Circuits
Ichiro Fujimori, Lorenzo Longo, Armond Hairapetian, Kazushi Seiyama, Steve Kosic, Jun Cao, Shu-Lap Chan