| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2025 | J | jnl |
IEEE J. Solid State Circuits
|
| 2025 | J | jnl |
IEEE Access
|
| 2024 | — | conf |
PETRA
|
| 2022 | — | conf |
AICAS
|
| 2020 | J | jnl |
J. Inf. Process. Syst.
|
| 2020 | — | conf |
ISOCC
|
| 2017 | — | conf |
ISSCC
|
| 2015 | J | jnl |
A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation.
IEEE J. Solid State Circuits
|
| 2012 | — | conf |
IAS (2)
|
| 2010 | J | jnl |
Comput. Ind.
|
| 2010 | J | jnl |
Wirel. Sens. Netw.
|