Jun-Hyun Bae

12 papers A* 1Journal 6Unranked 5
YearRankTypeTitle / Venue / Authors
2026 A* conf
Mechanistic Dissection of Cross-Attention Subspaces in Text-to-Image Diffusion Models.
AAAI
Jun-Hyun Bae, Wonyong Jo, Jaehyup Lee, Heechul Jung
2024 — conf
Adaptive Bias Discovery for Learning Debiased Classifier.
ACCV (8)
Jun-Hyun Bae, Minho Lee, Heechul Jung
2024 — conf
Invariant Risk Minimization in Medical Imaging with Modular Data Representation.
ICEIC
Jun-Hyun Bae, Chanwoo Kim, Tae-Young Chang
2022 — conf
Learning Associative Reasoning Towards Systematicity Using Modular Networks.
ICONIP (2)
Jun-Hyun Bae, Taewon Park, Minho Lee
2021 J jnl
Meta-Learned Invariant Risk Minimization.
CoRR
Jun-Hyun Bae, Inchul Choi, Minho Lee
2016 J jnl
A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs.
IEEE Trans. Circuits Syst. II Express Briefs
Ji-Hoon Lim, Jun-Hyun Bae, Jaemin Jang, Hae-Kang Jung, Hyunbae Lee, Yongju Kim, Byungsub Kim, Jae-Yoon Sim, Hong-June Park
2013 J jnl
Effective Fixed-Point Pipelined Divider for Mobile Rendering Processors.
IEICE Trans. Inf. Syst.
Yong-Jin Park, Woo-Chan Park, Jun-Hyun Bae, Jin-Hong Park, Tack-Don Han
2010 J jnl
A Digital Differential Transmitter with Pseudo-LVDS Output Driver and Digital Mismatch Calibration.
IEICE Trans. Electron.
Jun-Hyun Bae, Sang-Hune Park, Jae-Yoon Sim, Hong-June Park
2010 — conf
A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel.
CICC
Jun-Hyun Bae, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Jae-Yoon Sim, Hong-June Park
2007 J jnl
An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator.
IEICE Trans. Electron.
Young-Chan Jang, Jun-Hyun Bae, Sang-Hune Park, Jae-Yoon Sim, Hong-June Park
2007 — conf
An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface.
CICC
Jun-Hyun Bae, Jin-Ho Seo, Hwan-Seok Yeo, Jae-Whui Kim, Jae-Yoon Sim, Hong-June Park
2006 J jnl
A Digital CMOS PWCL With Fixed-Delay Rising Edge and Digital Stability Control.
IEEE Trans. Circuits Syst. II Express Briefs
Young-Chan Jang, Jun-Hyun Bae, Hong-June Park