Jun-Hyeok Yang

13 papers Journal 5Unranked 8
YearRankTypeTitle / Venue / Authors
2026 — conf
A 0.6V 625um
ISSCC
Haejung Choi, Jooseong Kim, Woojoong Jung, Sungmin Yoo, Jun-Hyeok Yang, Sunghyuck Lee, Jihye Park, Michael Choi, Ben Rhew
2025 — conf
21.6 A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC.
ISSCC
Jeong-Hun Kim, Young-Jun Jeon, Won-Gyu Kim, Jaeseung Lee, Jun-Hyeok Yang, Sung-Wan Hong
2025 J jnl
A 0.5-1-V Time-Voltage Hybrid Domain Dual- Loop Analog LDO With Wide-Bandwidth High PSR in 28 nm.
IEEE J. Solid State Circuits
Jun-Hwan Jang, Hui-Dong Gwon, Sungmin Yoo, Jun-Hyeok Yang, Byong-Deok Choi
2025 J jnl
A Reconfigurable 3-Level Buck Converter With Supply Voltage Dynamic Split for Loop-Free Rapid V
IEEE Trans. Circuits Syst. II Express Briefs
Hyunjun Park, Minsu Kim, Woojoong Jung, Junho Song, Sungmin Yoo, Jun-Hyeok Yang, Michael Choi, Jongshin Shin, Hyung-Min Lee
2025 J jnl
A Robust High On-Duty Buck Converter Achieving a Peak Effective On-Duty of 0.976 With EMI Suppression.
IEEE Trans. Ind. Electron.
Young-Ju Oh, Chan-Ho Lee, Sang-Yun Nam, Jun-Seok Oh, Seok-Jun Lee, Jun-Hyeok Yang, Jaeseung Lee, Sung-Wan Hong
2024 — conf
8.8 A 97.18% Peak-Efficiency Asymmetrically Implemented Dual-phase (AID) Converter with a full Voltage-Conversion Ratio (VCR) between 0-and-1.
ISSCC
Hyo-Jin Park, Joo-Mi Cho, Chan-Ho Lee, Young-Ju Oh, Hyunwoo Jeong, Jun-Hyeok Yang, Jaeseung Lee, Sung-Wan Hong
2024 — conf
A 7V/μs-DVS Class-G Digital-Shunt-Aided Buck Voltage Regulator Achieving a 7% Dynamic-Efficiency Drop at a 600kHz DVS Occurrence Frequency in 28nm CMOS.
CICC
Hong-Hyun Bae, Jeong-Hyun Cho, Kihyun Kim, Seunghwa Shin, Doojin Jang, Jun-Hyeok Yang, Hyun-Sik Kim
2024 J jnl
A Fully Integrated Multi-Phase Voltage Regulator With Flying-Capacitor-Based Inter-Inductor Current Self-Balancing Scheme and Charge-Recycling Gate Driver.
IEEE J. Solid State Circuits
Jeong-Hyun Cho, Hong-Hyun Bae, Gyu-Wan Lim, Tae-Hwang Kong, Jun-Hyeok Yang, Hyun-Sik Kim
2022 J jnl
A 0.5-1 V, -68 dB Power Supply Rejection Capacitorless Analog LDO Using Voltage-to-Time Conversion in 28-nm CMOS.
IEEE J. Solid State Circuits
Jun-Hwan Jang, Hui-Dong Gwon, Tae-Hwang Kong, Jun-Hyeok Yang, Byong-Deok Choi
2022 — conf
A 0.65V 1316µm
ISSCC
Junghyun Park, Jooseong Kim, Kwangho Kim, Jun-Hyeok Yang, Michael Choi, Jongshin Shin
2022 — conf
A Fully-Integrated 0.9W/mm
VLSI Technology and Circuits
Jeong-Hyun Cho, Hong-Hyun Bae, Gyu-Wan Lim, Tae-Hwang Kong, Jun-Hyeok Yang, Hyun-Sik Kim
2022 — conf
A Hybrid Always-Dual-Path Recursive Step-Down Converter Using Adaptive Switching Level Control Achieving 95.4% Efficiency with 288mΩ Large-DCR Inductor.
CICC
Woojoong Jung, Minsu Kim, Hyunjun Park, Sungmin Yoo, Tae-Hwang Kong, Jun-Hyeok Yang, Michael Choi, Jongshin Shin, Hyung-Min Lee
2021 — conf
29.6 A Distributed Digital LDO with Time-Multiplexing Calibration Loop Achieving 40A/mm2 Current Density and 1mA-to-6.4A Ultra-Wide Load Range in 5nm FinFET CMOS.
ISSCC
Dong-Hoon Jung, Tae-Hwang Kong, Jun-Hyeok Yang, Sangho Kim, Kwangho Kim, Jeongpyo Park, Michael Choi, Jongshin Shin