Julio Villalba

50 papers A 2B 3C 6Misc 1Journal 21Unranked 17

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Floating Point HUB Adder for RISC-V Sargantana Processor. CoRR Gerardo Bandera, Javier Salamero, Miquel Moretó, Julio Villalba
2024	J	`jnl`	Teaching Experiences using the RVfpga Package. CoRR Daniel Chaver, Sarah L. Harris, Luis Piñuel, Olof Kindgren, Roy Kravitz, José Ignacio Gómez, Fernando Castro, Katzalin Olcoz, Julio Villalba, Alexander Grinshpun, Freddy Gabbay, Nicholas Luke Seed, Rui Policarpo Duarte, Manuel López, Óscar Alonso, Robert Owen
2022	J	`jnl`	High-Radix Formats for Enhancing Floating-Point FPGA Implementations. Circuits Syst. Signal Process. Julio Villalba, Javier Hormigo
2019	J	`jnl`	Fast HUB Floating-Point Adder for FPGA. IEEE Trans. Circuits Syst. II Express Briefs Julio Villalba, Javier Hormigo, Sonia González-Navarro
2017	J	`jnl`	HUB Floating Point for Improving FPGA Implementations of DSP Applications. IEEE Trans. Circuits Syst. II Express Briefs Javier Hormigo, Julio Villalba
2016	J	`jnl`	Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest. IEEE Trans. Very Large Scale Integr. Syst. Javier Hormigo, Julio Villalba
2016	J	`jnl`	New Formats for Computing with Real-Numbers under Round-to-Nearest. IEEE Trans. Computers Javier Hormigo, Julio Villalba
2015	—	`conf`	Simplified floating-point units for high dynamic range image and video systems. ISCE Javier Hormigo, Julio Villalba
2014	Misc	`conf`	Optimizing DSP circuits by a new family of arithmetic operators. ACSSC Javier Hormigo, Julio Villalba
2013	C	`conf`	Efficient floating-point representation for balanced codes for FPGA devices. ICCD Julio Villalba, Javier Hormigo, Francisco Corbera, Mario A. González, Emilio L. Zapata
2013	J	`jnl`	Multioperand Redundant Adders on FPGAs. IEEE Trans. Computers Javier Hormigo, Julio Villalba, Emilio L. Zapata
2012	—	`conf`	Decimal online multioperand addition. ACSCC Carlos Garcia-Vega, Sonia González-Navarro, Julio Villalba, Emilio L. Zapata
2012	J	`jnl`	Radix-2 Multioperand and Multiformat Streaming Online Addition. IEEE Trans. Computers Julio Villalba, Tomás Lang, Javier Hormigo
2011	J	`jnl`	High-Speed Algorithms and Architectures for Range Reduction Computation. IEEE Trans. Very Large Scale Integr. Syst. Francisco J. Jaime, M. A. Sánchez, Javier Hormigo, Julio Villalba, Emilio L. Zapata
2010	J	`jnl`	Enhanced Scaling-Free CORDIC. IEEE Trans. Circuits Syst. I Regul. Pap. Francisco J. Jaime, Miguel A. Sanchez, Javier Hormigo, Julio Villalba, Emilio L. Zapata
2010	—	`conf`	UCORE: Reconfigurable Platform for Educational Purposes. ReConFig Francisco J. Quiles, Manuel Ortiz, María Brox, Carlos Diego Moreno-Moreno, Javier Hormigo, Julio Villalba
2009	C	`conf`	Computation of Decimal Transcendental Functions Using the CORDIC Algorithm. IEEE Symposium on Computer Arithmetic Álvaro Vázquez, Julio Villalba, Elisardo Antelo
2009	—	`conf`	Efficient Implementation of Carry-Save Adders in FPGAs. ASAP Javier Hormigo, Manuel Ortiz, Francisco J. Quiles, Francisco J. Jaime, Julio Villalba, Emilio L. Zapata
2009	—	`conf`	Efficient mapping on FPGA of convolution computation based on combined CSA-CPA accumulator. ICECS Carlos Diego Moreno-Moreno, Francisco J. Quiles, Manuel Ortiz, María Brox, Javier Hormigo, Julio Villalba, Emilio L. Zapata
2008	J	`jnl`	A Low-Latency Pipelined 2D and 3D CORDIC Processors. IEEE Trans. Computers Elisardo Antelo, Julio Villalba, Emilio L. Zapata
2008	B	`conf`	New SIMD instructions set for image processing applications enhancement. ICIP Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata
2008	J	`jnl`	Pipelined Architecture for Additive Range Reduction. J. Signal Process. Syst. Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata
2008	C	`conf`	SIMD Enhancements for a Hough Transform Implementation. DSD Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata
2007	—	`conf`	Improving the Throughput of On-line Addition for Data Streams. ASAP Julio Villalba, Javier Hormigo, Tomás Lang
2006	J	`jnl`	Double-Residue Modular Range Reduction for Floating-Point Hardware Implementations. IEEE Trans. Computers Julio Villalba, Tomás Lang, Mario A. González
2006	B	`conf`	Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA. FPL Joaquín Olivares, Ignacio Benavides, Javier Hormigo, Julio Villalba, Emilio L. Zapata
2006	—	`conf`	Pipelined Range Reduction for Floating Point Numbers. ASAP Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata
2006	J	`jnl`	SAD computation based on online arithmetic for motion estimation. Microprocess. Microsystems Joaquín Olivares, Javier Hormigo, Julio Villalba, Ignacio Benavides, Emilio L. Zapata
2005	C	`conf`	Low Latency Pipelined Circular CORDIC. IEEE Symposium on Computer Arithmetic Elisardo Antelo, Julio Villalba
2005	—	`conf`	On-line Multioperand Addition Based on On-line Full Adders. ASAP Julio Villalba, Javier Hormigo, Jose M. Prades, Emilio L. Zapata
2004	J	`jnl`	CORDIC Processor for Variable-Precision Interval Arithmetic. J. VLSI Signal Process. Javier Hormigo, Julio Villalba, Emilio L. Zapata
2004	A	`conf`	Evaluation of Elementary Functions Using Multimedia Features. IPDPS Gerardo Bandera, Mario A. González, Julio Villalba, Javier Hormigo, Emilio L. Zapata
2004	B	`conf`	Minimum Sum of Absolute Differences Implementation in a Single FPGA Device. FPL Joaquín Olivares, Javier Hormigo, Julio Villalba, Ignacio Benavides
2002	—	`conf`	Polynomial Evaluation on Multimedia Processors. ASAP Julio Villalba, Gerardo Bandera, Mario A. González, Javier Hormigo, Emilio L. Zapata
2000	—	`conf`	A Hardware Algorithm for Variable-Precision Logarithm. ASAP Javier Hormigo, Julio Villalba, Michael J. Schulte
2000	A	`conf`	MMX-Like Architecture Extension to Support the Rotation Operation. IEEE International Conference on Multimedia and Expo (III) Julio Villalba, Javier Hormigo, Mario A. González, Emilio L. Zapata
1999	—	`conf`	Arithmetic Unit for the Computation of Interval Elementary Functions. EUROMICRO Javier Hormigo, Julio Villalba, Emilio L. Zapata
1999	C	`conf`	Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm. IEEE Symposium on Computer Arithmetic Javier Hormigo, Julio Villalba, Emilio L. Zapata
1998	—	`conf`	A Hardware Approach to Interval Arithmetic for Sine and Cosine Functions. SCAN Javier Hormigo, Julio Villalba, Emilio L. Zapata
1998	J	`jnl`	Parallel Compensation of Scale Factor for the CORDIC Algorithm. J. VLSI Signal Process. Julio Villalba, Tomás Lang, Emilio L. Zapata
1998	J	`jnl`	Radix-4 Vectoring CORDIC Algorithm and Architectures. J. VLSI Signal Process. Julio Villalba, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera
1997	J	`jnl`	High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm. IEEE Trans. Computers Elisardo Antelo, Julio Villalba, Javier D. Bruguera, Emilio L. Zapata
1997	—	`conf`	Low latency word serial CORDIC. ASAP Julio Villalba, Tomás Lang
1996	J	`jnl`	Cordic based parallel/pipelined architecture for the Hough transform. J. VLSI Signal Process. Javier D. Bruguera, Nicolás Guil, Tomás Lang, Julio Villalba, Emilio L. Zapata
1996	—	`conf`	High Radix Cordic Rotation Based on Selection by Rounding. Euro-Par, Vol. II Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Julio Villalba, Emilio L. Zapata
1996	—	`conf`	Radix-4 Vectoring Cordic Algorithm And Architectures. ASAP Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera
1995	J	`jnl`	A fast Hough transform for segment detection. IEEE Trans. Image Process. Nicolás Guil, Julio Villalba, Emilio L. Zapata
1995	—	`conf`	CORDIC Architectures with Parallel Compensation of the Scale Factor. ASAP Julio Villalba, José Antonio Hidalgo López, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera
1995	—	`conf`	Digit On-line Large Radix CORDIC Rotator. ASAP Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata
1995	C	`conf`	Redundant CORDIC Rotator Based on Parallel Prediction. IEEE Symposium on Computer Arithmetic Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata