Julien Ryckaert

85 papers A* 3A 7C 10Journal 21Unranked 44

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	3D IGZO Charge-Coupled Memory DTCO & STCO Analysis for Compute-near-Memory Applications. ISCAS Bowen Wang, Khakim Akhunov, Hyungrock Oh, Fernando García-Redondo, Yukai Chen, Arvind Sharma, Jiacong Sun, Sahan Gamage, Maarten Rosmeulen, Swaraj Bandhu Mahato, Rishabh Kishore, Subhali Subhechha, Jaydeep P. Kulkarni, Marian Verhelst, Dwaipayan Biswas, Marie Garcia Bardon, Wim Dehaene, Julien Ryckaert
2025	C	`conf`	3D SRAM Disaggregation in Advanced CMOS Nodes using Hybrid Bonding Technology. ISCAS Bhawana Kumari, Anurag Swarnkar, Dawit Burusie Abdi, Fernando García-Redondo, James Myers, Julien Ryckaert, Jaydeep P. Kulkarni, Dwaipayan Biswas
2025	J	`jnl`	Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC. IEEE Trans. Very Large Scale Integr. Syst. Sudipta Das, Samuel Riedel, Mohamed Naeim, Moritz Brunion, Marco Bertuletti, Luca Benini, Julien Ryckaert, James Myers, Dwaipayan Biswas, Dragomir Milojevic
2025	J	`jnl`	CMOS 2.0 - Redefining the Future of Scaling. CoRR Moritz Brunion, Navaneeth Kunhi Purayil, Francesco Dell'Atti, Sebastian Lam, Refik Bilgic, Mehdi B. Tahoori, Luca Benini, Julien Ryckaert
2025	—	`conf`	Design Technology Co-Optimization of 3D SRAM Macro in Nanosheet Technology for High-Bandwidth Applications. IMW Anurag Swarnkar, Dawit Burusie Abdi, Bhawana Kumari, Priya Venugopal, Nicolas Pantano, Geert Hellings, Jaydeep P. Kulkarni, Dwaipayan Biswas, Julien Ryckaert, Fernando García-Redondo
2025	C	`conf`	Framework for Augmenting Main Memory with CXL-connected Emerging Memory Alternatives. ISCAS Khakim Akhunov, Dwaipayan Biswas, Emil Karimov, Arvind Sharma, Hyungrock Oh, Maarten Rosmeulen, Julien Ryckaert, James Myers
2025	A	`conf`	Half-Height Double-Row CFET Standard Cells for Area Optimized Placement in A7 CMOS Node. ICCAD Halil Kükner, Ji-Yung Lin, Sheng Yang, Lynn Verschueren, Jürgen Bömmels, Anita Farokhnejad, Maarten Van De Put, Odysseas Zografos, Naoto Horiguchi, Geert Hellings, Marie Garcia Bardon, Julien Ryckaert
2025	A	`conf`	Invited Paper: CMOS 2.0 - Redefining the Future of Scaling. ICCAD Moritz Brunion, Navaneeth Kunhi Purayil, Francesco Dell'Atti, Sebastian Lam, Refik Bilgic, Mehdi B. Tahoori, Luca Benini, Julien Ryckaert
2025	A	`conf`	Late Breaking Results: Thermal Feasibility of Backside Integrated LDOs in 2.5D/3D System-in-Package Using Nanosheet Technology. DATE Yukai Chen, Subrat Mishra, Julien Ryckaert, Dwaipayan Biswas, James Myers
2025	C	`conf`	Live Demonstration: N2 Nanosheet Pathfinding-PDK. ISCAS Chaohan Wang, Jack Cousins, Anita Farokhnejad, Marie Garcia Bardon, Julien Ryckaert
2025	J	`jnl`	Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes. CoRR Lorenzo Ruotolo, Lara Orlandic, Pengbo Yu, Moritz Brunion, Daniele Jahier Pagliari, Dwaipayan Biswas, Giovanni Ansaloni, David Atienza, Julien Ryckaert, Francky Catthoor, Yukai Chen
2025	J	`jnl`	Thermal Implications of Non-Uniform Power in BSPDN-Enabled 2.5D/3D Chiplet-based Systems-in-Package using Nanosheet Technology. CoRR Yukai Chen, Massimiliano Di Todaro, Bjorn Vermeersch, Herman Oprins, Daniele Jahier Pagliari, Julien Ryckaert, Dwaipayan Biswas, James Myers
2024	C	`conf`	3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs. ISCAS Sudipta Das, Samuel Riedel, Marco Bertuletti, Luca Benini, Moritz Brunion, Julien Ryckaert, James Myers, Dwaipayan Biswas, Dragomir Milojevic
2024	—	`conf`	Accelerating Large Language Model Training with In-Package Optical Links for Scale-Out Systems. ISVLSI Aakash Patel, Dwaipayan Biswas, Joyjit Kundu, Yoojin Ban, Nicolas Pantano, Arindam Mallik, Julien Ryckaert, James Myers
2024	—	`conf`	Backside Power Delivery in High Density and High Performance Context: IR-Drop and Block-Level Power-Performance-Area Benefits. VLSI Technology and Circuits Yun Zhou, S. C. Song, Halil Kükner, Giuliano Sisto, Sheng Yang, Anita Farokhnejad, Mohamed Naeim, Moritz Brunion, Ji-Yung Lin, Odysseas Zografos, Pieter Weckx, Shashank Ekbote, Nick Stevens-Yu, David Greenlaw, Steve Molloy, Geert Hellings, Julien Ryckaert
2024	J	`jnl`	Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect. IEEE Trans. Circuits Syst. I Regul. Pap. Hsiao-Hsuan Liu, Carlo Gilardi, Shairfe Muhammad Salahuddin, Zhenlin Pei, Pieter Schuddinck, Yang Xiang, Pieter Weckx, Geert Hellings, Marie Garcia Bardon, Julien Ryckaert, Chenyun Pan, Subhasish Mitra, Francky Catthoor
2024	A*	`conf`	GNN-assisted Back-side Clock Routing Methodology for Advance Technologies. DAC Nesara Eranna Bethur, Pruek Vanna-Iampikul, Odysseas Zografos, Lingjun Zhu, Giuliano Sisto, Dragomir Milojevic, Alberto García Ortiz, Geert Hellings, Julien Ryckaert, Francky Catthoor, Sung Kyu Lim
2024	J	`jnl`	Multidie 3-D Stacking of Memory Dominated Neuromorphic Architectures. IEEE Trans. Very Large Scale Integr. Syst. Leandro Mateus Giacomini Rocha, Refik Bilgic, Mohamed Naeim, Sudipta Das, Herman Oprins, Amirreza Yousefzadeh, Mario Konijnenburg, Dragomir Milojevic, James Myers, Julien Ryckaert, Dwaipayan Biswas
2024	—	`conf`	On-chip Memory in Accelerator-based Systems: A System Technology Co-Optimization (STCO) Perspective for Emerging Device Technologies. SOCC Siva Satyendra Sahoo, Dawit Burusie Abdi, Julien Ryckaert, James Myers, Dwaipayan Biswas
2024	—	`conf`	STCO: Driving the More than Moore Era. ISVLSI Dwaipayan Biswas, James Myers, Srikanth B. Samavedam, Julien Ryckaert
2024	A	`conf`	Smoothing Disruption Across the Stack: Tales of Memory, Heterogeneity, & Compilers. DATE Michael T. Niemier, Zephan M. Enciso, M. Sharifi, Xiaobo Sharon Hu, Ian O'Connor, A. Graening, R. Sharma, P. Gupta, Jerónimo Castrillón, João Paulo C. de Lima, Asif Ali Khan, Hamid Farzaneh, N. Afroze, Asif Khan, Julien Ryckaert
2024	—	`conf`	Thermal Analysis of High-Performance Server SoCs from FinFET to Nanosheet Technologies. IRPS Nitish Kumar, Sankatali Venkateswarlu, Yukai Chen, Moritz Brunion, Subrat Mishra, Ankur Gupta, Pushpapraj Singh, Francky Catthoor, James Myers, Julien Ryckaert, Dwaipayan Biswas
2024	—	`conf`	Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5). VLSI Technology and Circuits S. Mishra, Bjorn Vermeersch, Sankatali Venkateswarlu, Halil Kukner, Gioele Mirabelli, Fabian M. Bufler, Moritz Brunion, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Francky Catthoor, Pieter Weckx, Geert Hellings, James Myers, Julien Ryckaert
2024	—	`conf`	Thermal Implications in Scaling High-Performance Server 3D Chiplet-Based 2.5D SoC from FinFET to Nanosheet. ISVLSI Yukai Chen, Sankatali Venkateswarlu, Subrat Mishra, Julien Ryckaert, James Myers, Dwaipayan Biswas
2024	—	`conf`	Thermal Performance Evaluation of Multi-Core SOCs Using Power-Thermal Co-Simulation. IRPS Subrat Mishra, Bjorn Vermeersch, Sankatali Venkateswarlu, Halil Kukner, A. Sharma, G. Mirabeli, Fabian M. Bufler, Moritz Brunion, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Francky Catthoor, Pieter Weckx, Geert Hellings, James Myers, Julien Ryckaert
2023	J	`jnl`	3D SRAM Macro Design in 3D Nanofabric Process Technology. IEEE Trans. Circuits Syst. I Regul. Pap. Dawit Burusie Abdi, Shairfe Muhammad Salahuddin, Jürgen Bömmels, Edouard Giacomin, Pieter Weckx, Julien Ryckaert, Geert Hellings, Francky Catthoor
2023	—	`conf`	Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node. VLSI Technology and Circuits Giuliano Sisto, R. Preston, Rongmei Chen, Gioele Mirabelli, Anita Farokhnejad, Yun Zhou, Ivan Ciofi, Anne Jourdain, A. Veloso, Michele Stucchi, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert
2023	C	`conf`	Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications. ISCAS Mohit Kumar Gupta, Manu Perumkunnil, Dwaipayan Biswas, Saeideh Alinezhad Chamazcoti, Gouri Sankar Kar, Arnaud Furnémont, Julien Ryckaert
2023	C	`conf`	Impact of interconnects enhancement on SRAM design beyond 5nm technology node. ISCAS Mohit Kumar Gupta, Pieter Weckx, Manu Perumkunnil Komalan, Julien Ryckaert
2023	—	`conf`	MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array. ICECS Carlos Escuin, Fernando García-Redondo, Mahdi Zahedi, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, José María Llabería, James Myers, Julien Ryckaert, Dwaipayan Biswas, Francky Catthoor
2023	—	`conf`	PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology. VLSI Technology and Circuits S. Yang, Pieter Schuddinck, Marie Garcia Bardon, Yang Xiang, Anabela Veloso, B. T. Chan, Gioele Mirabelli, Gaspard Hiblot, Geert Hellings, Julien Ryckaert
2023	—	`conf`	Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs). IRPS Subrat Mishra, Sankatali Venkateswarlu, Bjorn Vermeersch, Moritz Brunion, Melina Lofrano, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Gaspard Hiblot, Geert Van der Plas, Pieter Weckx, Geert Hellings, James Myers, Francky Catthoor, Julien Ryckaert
2022	—	`conf`	Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. VLSI Technology and Circuits Rongmei Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, Anabela Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne
2022	A	`conf`	Design enablement of CFET devices for sub-2nm CMOS nodes. DATE Odysseas Zografos, Bilal Chehab, Pieter Schuddinck, Gioele Mirabelli, Naveen Kakarla, Yang Xiang, Pieter Weckx, Julien Ryckaert
2022	—	`conf`	Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO. VLSI Technology and Circuits Kateryna Serbulova, S.-H. Chen, Geert Hellings, Anabela Veloso, Anne Jourdain, Dimitri Linten, Jo De Boeck, Guido Groeseneken, Julien Ryckaert, Geert Van der Plas, Eric Beyne, Eugenio Dentoni Litta, Naoto Horiguchi
2022	J	`jnl`	Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era. IEEE Trans. Very Large Scale Integr. Syst. Giuliano Sisto, Odysseas Zografos, Bilal Chehab, Naveen Kakarla, Yang Xiang, Dragomir Milojevic, Pieter Weckx, Geert Hellings, Julien Ryckaert
2022	—	`conf`	PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch. VLSI Technology and Circuits Pieter Schuddinck, Fabian M. Bufler, Yang Xiang, Anita Farokhnejad, Gioele Mirabelli, Anne Vandooren, Bilal Chehab, A. Gupta, César Roda Neve, Geert Hellings, Julien Ryckaert
2022	—	`conf`	Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. VLSI Technology and Circuits Anabela Veloso, Anne Jourdain, D. Radisic, Rongmei Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, Filip Schleicher, F. Sebaai, Yusuke Oniki, X. Zhou, A. Gupta, Tom Schram, B. Briggs, C. Lorant, E. Rosseel, Andriy Hikavyy, Roger Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, Katia Devriendt, B. T. Chan, S. Demuynck, Gaspard Hiblot, Geert Van der Plas, Julien Ryckaert, Gerald Beyer, E. Dentoni Litta, Eric Beyne, Naoto Horiguchi
2022	—	`conf`	Self-Heating in iN8-iN2 CMOS Logic Cells: Thermal Impact of Architecture (FinFET, Nanosheet, Forksheet and CFET) and Scaling Boosters. VLSI Technology and Circuits Bjorn Vermeersch, Erik Bury, Yang Xiang, Pieter Schuddinck, Krishna K. Bhuwalka, Geert Hellings, Julien Ryckaert
2021	—	`conf`	Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks. ESSCIRC Amita Rawat, Krishna K. Bhuwalka, Philippe Matagne, Bjorn Vermeersch, Hao Wu, Geert Hellings, Julien Ryckaert, Changze Liu
2021	—	`conf`	Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks. ESSDERC Amita Rawat, Krishna K. Bhuwalka, Philippe Matagne, Bjorn Vermeersch, Hao Wu, Geert Hellings, Julien Ryckaert, Changze Liu
2020	—	`conf`	3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs. VLSI-SoC (Selected Papers) Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon
2020	—	`conf`	Device Scaling roadmap and its implications for Logic and Analog platform. BCICTS Alessio Spessot, Bertrand Parvais, Amita Rawat, Kenichi Miyaguchi, Pieter Weckx, Doyoung Jang, Julien Ryckaert
2020	J	`jnl`	Heterogeneous 3D Integration for a RISC-V System With STT-MRAM. IEEE Comput. Archit. Lett. Lingjun Zhu, Lennart Bamberg, Anthony Agnesina, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Julien Ryckaert, Alberto García-Ortiz, Sung Kyu Lim
2020	C	`conf`	Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow. VLSI-SOC Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon
2019	A*	`conf`	Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications. DAC Trong Huynh Bao, Anabela Veloso, Sushil Sakhare, Philippe Matagne, Julien Ryckaert, Manu Perumkunnil, Davide Crotti, Farrukh Yasin, Alessio Spessot, Arnaud Furnémont, Gouri Sankar Kar, Anda Mocuta
2017	—	`conf`	SRAM designs for 5nm node and beyond: Opportunities and challenges. ICICDT Trong Huynh Bao, Sushil Sakhare, Julien Ryckaert, Alessio Spessot, Diederik Verkest, Anda Mocuta
2017	J	`jnl`	Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond. IEEE Trans. Very Large Scale Integr. Syst. Trong Huynh Bao, Julien Ryckaert, Zsolt Tokei, Abdelkarim Mercha, Diederik Verkest, Aaron Voon-Yew Thean, Piet Wambacq
2016	—	`conf`	Scaling Beyond 7nm: Design-Technology Co-optimization at the Rescue. ISPD Julien Ryckaert
2015	—	`conf`	Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM. ICICDT Trong Huynh Bao, Sushil Sakhare, Julien Ryckaert, Dmitry Yakimets, Abdelkarim Mercha, Diederik Verkest, Aaron Voon-Yew Thean, Piet Wambacq
2015	—	`conf`	Holisitic device exploration for 7nm node. CICC Praveen Raghavan, Marie Garcia Bardon, Doyoung Jang, P. Schuddinck, Dmitry Yakimets, Julien Ryckaert, Abdelkarim Mercha, Naoto Horiguchi, Nadine Collaert, Anda Mocuta, Dan Mocuta, Zsolt Tokei, Diederik Verkest, Aaron Thean, An Steegen
2015	A	`conf`	Impact of interconnect multiple-patterning variability on SRAMs. DATE Ioannis Karageorgos, Michele Stucchi, Praveen Raghavan, Julien Ryckaert, Zsolt Tokei, Diederik Verkest, Rogier Baert, Sushil Sakhare, Wim Dehaene
2014	—	`conf`	Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. ESSDERC Trong Huynh Bao, Dmitry Yakimets, Julien Ryckaert, Ivan Ciofi, Rogier Baert, Anabela Veloso, Jürgen Bömmels, Nadine Collaert, Philippe Roussel, S. Demuynck, Praveen Raghavan, Abdelkarim Mercha, Zsolt Tokei, Diederik Verkest, Aaron Thean, Piet Wambacq
2014	—	`conf`	Design Technology co-optimization for N10. CICC Julien Ryckaert, Praveen Raghavan, Rogier Baert, Marie Garcia Bardon, Mircea Dusa, Arindam Mallik, Sushil Sakhare, Boris Vandewalle, Piet Wambacq, Bharani Chava, Kris Croes, Morin Dehan, Doyoung Jang, Philippe Leray, Tsung-Te Liu, Kenichi Miyaguchi, Bertrand Parvais, Pieter Schuddinck, Philippe Weemaes, Abdelkarim Mercha, Jürgen Bömmels, Naoto Horiguchi, Greg McIntyre, Aaron Thean, Zsolt Tökei, Shaunee Cheng, Diederik Verkest, An Steegen
2014	C	`conf`	ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy. DSD Santhosh Kumar Rethinagiri, Oscar Palomar, Anita Sobe, Thomas Knauth, Wojciech M. Barczynski, Gulay Yalcin, Yarco Hayduk, Adrián Cristal, Osman S. Unsal, Pascal Felber, Christof Fetzer, Julien Ryckaert, Gina Alioto
2013	—	`conf`	Low-power, low-penalty, flip-chip integrated, 10Gb/s ring-based 1V CMOS photonics transmitter. OFC/NFOEC Michal Rakowski, Marianna Pantouvaki, Hui Yu, Wim Bogaerts, Kristin De Meyer, Michiel Steyaert, Bradley Snyder, Peter O'Brien, Julien Ryckaert, Philippe Absil, Joris Van Campenhout
2013	A*	`conf`	TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes. DAC Arindam Mallik, Paul Zuber, Tsung-Te Liu, Bharani Chava, Bhavana Ballal, Pablo Royer Del Bario, Rogier Baert, Kris Croes, Julien Ryckaert, Mustafa Badaroglu, Abdelkarim Mercha, Diederik Verkest
2012	—	`conf`	A calibrated pathfinding model for signal integrity analysis on interposer. CICC Jaemin Kim, Sunyoung Kim, Julien Ryckaert, Mikael Detalle, Nele Van Hoovels, Pol Marchal
2012	—	`conf`	Low-Power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator. CICC Michal Rakowski, Julien Ryckaert, Marianna Pantouvaki, Hui Yu, Wim Bogaerts, Kristin De Meyer, Michiel Steyaert, Philippe P. Absil, Joris Van Campenhout
2012	J	`jnl`	RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter. IEEE J. Solid State Circuits Ewout Martens, André Bourdoux, Aïssa Couvreur, Robert Fasthuber, Peter Van Wesemael, Geert Van der Plas, Jan Craninckx, Julien Ryckaert
2011	—	`conf`	DRAM-on-logic Stack - Calibrated thermal and mechanical models integrated into PathFinding flow. CICC Dragomir Milojevic, Herman Oprins, Julien Ryckaert, Paul Marchal, Geert Van der Plas
2010	J	`jnl`	A 0.5 mm IEEE J. Solid State Circuits Arnd Geis, Julien Ryckaert, Lynn Bos, Gerd Vandersteen, Yves Rolain, Jan Craninckx
2010	—	`conf`	A 100kHz-10MHz BW, 78-to-52dB DR, 4.6-to-11mW flexible SC ΣΔ modulator in 1.2-V 90-nm CMOS. ESSCIRC Alonso Morgado, Rocío del Río, José M. de la Rosa, Lynn Bos, Julien Ryckaert, Geert Van der Plas
2010	A	`conf`	An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation. DATE Arnd Geis, Pierluigi Nuzzo, Julien Ryckaert, Yves Rolain, Gerd Vandersteen, Jan Craninckx
2010	J	`jnl`	Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS. IEEE J. Solid State Circuits Lynn Bos, Gerd Vandersteen, Pieter Rombouts, Arnd Geis, Alonso Morgado, Yves Rolain, Geert Van der Plas, Julien Ryckaert
2009	J	`jnl`	A 2-mm IEEE J. Solid State Circuits Vito Giannini, Pierluigi Nuzzo, Charlotte Soens, Kameswaran Vengattaramane, Julien Ryckaert, Michaël Goffioul, Björn Debaillie, Jonathan Borremans, Joris Van Driessche, Jan Craninckx, Mark Ingels
2009	J	`jnl`	A 2.4 GHz Low-Power Sixth-Order RF Bandpass ΔΣ Converter in CMOS. IEEE J. Solid State Circuits Julien Ryckaert, Jonathan Borremans, Bob Verbruggen, Lynn Bos, Costantino Armiento, Jan Craninckx, Geert Van der Plas
2009	—	`conf`	A 2mm ISSCC Vito Giannini, Pierluigi Nuzzo, Charlotte Soens, Kameswaran Vengattaramane, Michiel Steyaert, Julien Ryckaert, Michaël Goffioul, Björn Debaillie, Joris Van Driessche, Jan Craninckx, Mark Ingels
2009	J	`jnl`	A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS. IEEE J. Solid State Circuits Jonathan Borremans, Julien Ryckaert, Claude Desset, Maarten Kuijk, Piet Wambacq, Jan Craninckx
2009	—	`conf`	A multirate 3.4-to-6.8mW 85-to-66dB DR GSM/bluetooth/UMTS cascade DT ΔΣM in 90nm digital CMOS. ISSCC Lynn Bos, Gerd Vandersteen, Julien Ryckaert, Pieter Rombouts, Yves Rolain, Geert Van der Plas
2008	—	`conf`	A Low Power, Reconfigurable IR-UWB System. ICC Marian Verhelst, Julien Ryckaert, Yves Vanderperren, Wim Dehaene
2008	—	`conf`	A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS. ESSCIRC Jonathan Borremans, Julien Ryckaert, Piet Wambacq, Maarten Kuijk, Jan Craninckx
2007	J	`jnl`	A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a. IEEE J. Solid State Circuits Julien Ryckaert, Geert Van der Plas, Vincent De Heyn, Claude Desset, Bart van Poucke, Jan Craninckx
2007	—	`conf`	A 0.65-to-1.4nJ/burst 3-to-10GHz UWB Digital TX in 90nm CMOS for IEEE 802.15.4a. ISSCC Julien Ryckaert, Geert Van der Plas, Vincent De Heyn, Claude Desset, Geert Vanwijnsberghe, Bart van Poucke, Jan Craninckx
2007	J	`jnl`	A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication. IEEE J. Solid State Circuits Julien Ryckaert, Marian Verhelst, Mustafa Badaroglu, Stefano D'Amico, Vincent De Heyn, Claude Desset, Pierluigi Nuzzo, Bart van Poucke, Piet Wambacq, Andrea Baschirotto, Wim Dehaene, Geert Van der Plas
2007	—	`conf`	A fast start-up 3GHz-10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS. ESSCIRC Vincent De Heyn, Geert Van der Plas, Julien Ryckaert, Jan Craninckx
2007	—	`conf`	Optimized Signal Acquisition for Low-Complexity and Low-Power IR-UWB Transceivers. VTC Spring Claude Desset, Mustafa Badaroglu, Julien Ryckaert, Bart van Poucke
2006	—	`conf`	A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS. ISSCC Julien Ryckaert, Mustafa Badaroglu, Vincent De Heyn, Geert Van der Plas, Pierluigi Nuzzo, Andrea Baschirotto, Stefano D'Amico, Claude Desset, Hans Suys, Michael Libois, Bart van Poucke, Piet Wambacq, Bert Gyselinckx
2006	J	`jnl`	Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling. EURASIP J. Wirel. Commun. Netw. Mustafa Badaroglu, Claude Desset, Julien Ryckaert, Vincent De Heyn, Geert Van der Plas, Piet Wambacq, Bart van Poucke
2006	C	`conf`	Human++: Emerging Technology for Body Area Networks. VLSI-SoC Bert Gyselinckx, Ruud J. M. Vullers, Chris Van Hoof, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov
2006	—	`conf`	Human++: Emerging Technology for Body Area Networks. VLSI-SoC (Selected Papers) Julien Penders, Bert Gyselinckx, Ruud J. M. Vullers, Olivier Rousseaux, Mladen Berekovic, Michael De Nil, Chris Van Hoof, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov
2006	J	`jnl`	Ultra-wideband channel model for communication around the human body. IEEE J. Sel. Areas Commun. Andrew Fort, Julien Ryckaert, Claude Desset, Philippe De Doncker, Piet Wambacq, Leo Van Biesen
2005	—	`conf`	Human++: autonomous wireless sensors for body area networks. CICC Bert Gyselinckx, Chris Van Hoof, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov
2005	—	`conf`	Ultra wide-band body area channel model. ICC Andrew Fort, Claude Desset, Julien Ryckaert, Philippe De Doncker, Leo Van Biesen, Stéphane Donnay
2005	J	`jnl`	Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation. IEEE Trans. Circuits Syst. I Regul. Pap. Julien Ryckaert, Claude Desset, Andrew Fort, Mustafa Badaroglu, Vincent De Heyn, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Bart van Poucke, Bert Gyselinckx