Juinn-Dar Huang

94 papers A* 2A 10C 8Journal 29Unranked 44
YearRankTypeTitle / Venue / Authors
2026 J jnl
Expertfuse: A huffman tree-based gradual expert integration framework for MoE models.
Neural Networks
Yizeng Fang, Juinn-Dar Huang
2025 C conf
An Accurate and Compact Design Integrating Seven Common Nonlinear Functions in Deep Learning.
ISCAS
Jye-En Wu, Ting-Wei Hu, Chih-Yao Liang, Juinn-Dar Huang
2025 J jnl
Anomaly Detection for Hybrid Butterfly Subspecies via Probability Filtering.
CoRR
Bo-Kai Ruan, Yi-Zeng Fang, Hong-Han Shuai, Juinn-Dar Huang
2025 — conf
Codeword Decomposition and Recoding Based Lossless Model Compression Algorithm and Its VLSI Decompressor Design.
AICAS
Lyu-Ming Ho, Chih-Yao Liang, Juinn-Dar Huang
2024 C conf
A Hardware-Friendly Alternative to Softmax Function and Its Efficient VLSI Implementation for Deep Learning Applications.
ISCAS
Meng-Hsun Hsieh, Xuan-Hong Li, Yu-Hsiang Huang, Pei-Hsuan Kuo, Juinn-Dar Huang
2024 — conf
A Novel Number Representation and Its Hardware Support for Accurate Low-Bit Quantization on Large Recommender Systems.
AICAS
Yu-Da Chu, Pei-Hsuan Kuo, Lyu-Ming Ho, Juinn-Dar Huang
2024 J jnl
Diabetic foot ulcers segmentation challenge report: Benchmark and analysis.
Medical Image Anal.
Moi Hoon Yap, Bill Cassidy, Michal Byra, Ting-Yu Liao, Huahui Yi, Adrian Galdran, Yung-Han Chen, Raphael Brüngel, Sven Koitka, Christoph M. Friedrich, Yu-Wen Lo, Ching-Hui Yang, Kang Li, Qicheng Lao, Miguel Ángel González Ballester, Gustavo Carneiro, Yi-Jen Ju, Juinn-Dar Huang, Joseph M. Pappachan, Neil D. Reeves, Vishnu Chandrabalan, Darren Dancey, Connah Kendrick
2024 — conf
Enhancing Brain Tumor Segmentation with Deep Supervision and Attention Mechanisms: Advances in the nnU-Net Framework.
ISBI
Yi-Zeng Fang, Juinn-Dar Huang
2024 — conf
NYCU-NLP at EXIST 2024: Leveraging Transformers with Diverse Annotations for Sexism Identification in Social Networks.
CLEF (Working Notes)
Yi-Zeng Fang, Lung-Hao Lee, Juinn-Dar Huang
2024 J jnl
SMILE-UHURA Challenge - Small Vessel Segmentation at Mesoscopic Scale from Ultra-High Resolution 7T Magnetic Resonance Angiograms.
CoRR
Soumick Chatterjee, Hendrik Mattern, Marc Dörner, Alessandro Sciarra, Florian Dubost, Hannes Schnurre, Rupali Khatun, Chun-Chih Yu, Tsung-Lin Hsieh, Yi-Shan Tsai, Yi-Zeng Fang, Yung-Ching Yang, Juinn-Dar Huang, Marshall Xu, Siyu Liu, Fernanda L. Ribeiro, Saskia Bollmann, Karthikesh Varma Chintalapati, Chethan Radhakrishna, Sri Chandana Hudukula Ram Kumar, Raviteja Sutrave, Abdul Qayyum, Moona Mazher, Imran Razzak, Cristóbal Rodero, Steven Niederren, Fengming Lin, Yan Xia, Jiacheng Wang, Riyu Qiu, Liansheng Wang, Arya Yazdan Panah, Rosana El Jurdi, Guanghui Fu, Janan Arslan, Ghislain Vaillant, Romain Valabrègue, Didier Dormont, Bruno Stankoff, Olivier Colliot, Luisa Vargas, Isai Daniel Chacón, Ioannis Pitsiorlas, Pablo Arbeláez, Maria A. Zuluaga, Stefanie Schreiber, Oliver Speck, Andreas Nürnberger
2023 C conf
An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis.
VLSI-SoC
Shan-Hui Chou, Ting-Yun Hsiao, Jing-Yang Jou, Juinn-Dar Huang
2023 — conf
Configurable Multi-Precision Floating-Point Multiplier Architecture Design for Computation in Deep Learning.
AICAS
Pei-Hsuan Kuo, Yu-Hsiang Huang, Juinn-Dar Huang
2023 — conf
Hardware-Friendly Activation Function Designs and Its Efficient VLSI Implementations for Transformer-Based Applications.
AICAS
Yu-Hsiang Huang, Pei-Hsuan Kuo, Juinn-Dar Huang
2023 J jnl
Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization.
ACM Trans. Design Autom. Electr. Syst.
Ling-Yen Song, Chih-Yun Chou, Tung-Chieh Kuo, Chien-Nan Liu, Juinn-Dar Huang
2022 — conf
An SoC Integration Ready VLIW-Driven CNN Accelerator with High Utilization and Scalability.
AICAS
Chia-Heng Hu, I-Hao Tseng, Pei-Hsuan Kuo, Juinn-Dar Huang
2022 — conf
Capture the Devil in the Details via Partition-then-Ensemble on Higher Resolution Images.
DFUC@MICCAI
Yung-Han Chen, Yi-Jen Ju, Juinn-Dar Huang
2022 — conf
Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm.
ASP-DAC
Ling-Yen Song, Tung-Chieh Kuo, Ming-Hung Wang, Chien-Nan Jimmy Liu, Juinn-Dar Huang
2022 — conf
Hardware-Friendly Progressive Pruning Framework for CNN Model Compression using Universal Pattern Sets.
VLSI-DAT
Wei-Cheng Chou, Cheng-Wei Huang, Juinn-Dar Huang
2022 — conf
Performance Optimization for MLP Accelerators using ILP-Based On-Chip Weight Allocation Strategy.
VLSI-DAT
Kang-Yi Fan, Jyun-Hua Chen, Chien-Nan Liu, Juinn-Dar Huang
2021 J jnl
All-You-Can-Fit 8-Bit Flexible Floating-Point Format for Accurate and Memory-Efficient Inference of Deep Neural Networks.
CoRR
Cheng-Wei Huang, Tim-Wei Chen, Juinn-Dar Huang
2021 — conf
An Efficient and Low-Power MLP Accelerator Architecture Supporting Structured Pruning, Sparse Activations and Asymmetric Quantization for Edge Computing.
AICAS
Wei-Chen Lin, Ya-Chu Chang, Juinn-Dar Huang
2021 C conf
Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip.
DSD
Shuaijie Ying, Sudip Roy, Juinn-Dar Huang, Shigeru Yamashita
2021 J jnl
Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model.
ACM J. Emerg. Technol. Comput. Syst.
Chia-Cheng Wu, Yi-Hsiang Hu, Chia-Chun Lin, Yung-Chih Chen, Juinn-Dar Huang, Chun-Yao Wang
2021 — conf
Storage-Aware Scheduling Algorithm for Reservoir Switching Minimization on Digital Microfluidic Biochips.
VLSI-DAT
Ling-Yen Song, Chih-Shen Yeh, Chien-Nan Liu, Juinn-Dar Huang
2020 — conf
A Coarse-Grained Dual-Convolver Based CNN Accelerator with High Computing Resource Utilization.
AICAS
Yi Lu, Yi-Lin Wu, Juinn-Dar Huang
2020 C conf
High-Speed Power-Efficient Coarse-Grained Convolver Architecture using Depth-First Compression Scheme.
ISCAS
Yi-Lin Wu, Yi Lu, Juinn-Dar Huang
2020 J jnl
Storage-Aware Algorithms for Dilution and Mixture Preparation With Flow-Based Lab-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sukanta Bhattacharjee, Robert Wille, Juinn-Dar Huang, Bhargab B. Bhattacharya
2019 J jnl
Design Automation for Dilution of a Fluid Using Programmable Microfluidic Device-Based Biochips.
ACM Trans. Design Autom. Electr. Syst.
Ankur Gupta, Juinn-Dar Huang, Shigeru Yamashita, Sudip Roy
2019 C conf
Forecast-Based Sample Preparation Algorithm for Unbalanced Splitting Correction on DMFBs.
ICCD
Ling-Yen Song, Yi-Ling Chen, Yung-Chun Lei, Juinn-Dar Huang
2019 — conf
Reactant Minimization for Multi-Target Sample Preparation on Digital Microfluidic Biochips Using Network Flow Models.
VLSI-DAT
Kang-Yi Fan, Shigeru Yamashita, Juinn-Dar Huang
2019 — conf
Time-Constrained Sample Preparation Algorithm for Reactant Minimization on Digital Microfluidic Biochips.
ISVLSI
Ling-Yen Song, Yu-Ying Li, Yung-Chun Lei, Juinn-Dar Huang
2018 — conf
A Comprehensive Security System for Digital Microfluidic Biochips.
ITC-Asia
Chun-Yu Lin, Juinn-Dar Huang, Hailong Yao, Tsung-Yi Ho
2018 — conf
Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays.
ISVLSI
Chia-Cheng Wu, Kung-Han Ho, Juinn-Dar Huang, Chun-Yao Wang
2018 J jnl
Concentration-Resilient Mixture Preparation with Digital Microfluidic Lab-on-Chip.
ACM Trans. Embed. Comput. Syst.
Sukanta Bhattacharjee, Yi-Ling Chen, Juinn-Dar Huang, Bhargab B. Bhattacharya
2018 — conf
Multi-target Many-Reactant Sample Preparation for Reactant Minimization on Microfluidic Biochips.
ISVLSI
Yung-Chun Lei, Tien-Kuo Lin, Juinn-Dar Huang
2018 A conf
Storage-aware sample preparation using flow-based microfluidic Labs-on-Chip.
DATE
Sukanta Bhattacharjee, Robert Wille, Juinn-Dar Huang, Bhargab B. Bhattacharya
2018 C conf
Versatile Ring-Based Architecture and Synthesis Flow for General-Purpose Digital Microfluidic Biochips.
VLSI-SoC
Juinn-Dar Huang, Chia-Hung Liu, Wei-Hao Yang
2017 C conf
Defect-aware synthesis for reconfigurable single-electron transistor arrays.
VLSI-SoC
Juinn-Dar Huang, Yi-Hang Chen, Jia-Shin Lu
2017 J jnl
Dilution and Mixing Algorithms for Flow-Based Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sukanta Bhattacharjee, Sudip Poddar, Sudip Roy, Juinn-Dar Huang, Bhargab B. Bhattacharya
2016 J jnl
Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints.
ACM J. Emerg. Technol. Comput. Syst.
Yi-Hang Chen, Jian-Yu Chen, Juinn-Dar Huang
2016 — conf
Chain-based pin count minimization for general-purpose digital microfluidic biochips.
ASP-DAC
Yung-Chun Lei, Chen-Shing Hsu, Juinn-Dar Huang, Jing-Yang Jou
2016 — conf
Multi-objective sample preparation algorithm for microfluidic biochips supporting various mixing models.
SoCC
Yung-Chun Lei, Tung-Hsuan Lin, Juinn-Dar Huang
2016 — conf
Reactant cost minimization through target concentration selection on microfluidic biochips.
BioCAS
Yung-Chun Lei, Yi-Ling Chen, Juinn-Dar Huang
2015 — conf
ROBDD-based area minimization synthesis for reconfigurable single-electron transistor arrays.
VLSI-DAT
Yi-Hang Chen, Yang Chen, Juinn-Dar Huang
2015 J jnl
Reactant Minimization for Sample Preparation on Microfluidic Biochips With Various Mixing Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chia-Hung Liu, Kuo-Cheng Shen, Juinn-Dar Huang
2015 J jnl
Reactant Minimization in Sample Preparation on Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chia-Hung Liu, Ting-Wei Chiang, Juinn-Dar Huang
2015 J jnl
TherWare: Thermal-Aware Placement and Routing Framework for 3D FPGAs with Location-Based Heat Balance.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Ya-Shih Huang, Han-Yuan Chang, Juinn-Dar Huang
2015 A conf
Volume-oriented sample preparation for reactant minimization on flow-based microfluidic biochips with multi-segment mixers.
DATE
Chi-Mei Huang, Chia-Hung Liu, Juinn-Dar Huang
2014 A conf
Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints.
DATE
Yi-Hang Chen, Jian-Yu Chen, Juinn-Dar Huang
2014 J jnl
ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant Multiplication.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Bu-Ching Lin, Juinn-Dar Huang, Jing-Yang Jou
2014 J jnl
Probability-Based Static Scaling Optimization for Fixed Wordlength FFT Processors.
J. Inf. Sci. Eng.
Bu-Ching Lin, Ming-En Shih, Juinn-Dar Huang, Jing-Yang Jou
2014 — conf
Sample preparation for droplet-based microfluidics.
ISIC
Juinn-Dar Huang, Chia-Hung Liu
2014 — conf
Two-staged parallel layer-aware partitioning for 3D designs.
VLSI-DAT
Yi-Hang Chen, Yi-Ting Chen, Juinn-Dar Huang
2013 — conf
Graph-based optimal reactant minimization for sample preparation on digital microfluidic biochips.
VLSI-DAT
Ting-Wei Chiang, Chia-Hung Liu, Juinn-Dar Huang
2013 — conf
Latency-optimization synthesis with module selection for digital microfluidic biochips.
SoCC
Chia-Hung Liu, Kuang-Cheng Liu, Juinn-Dar Huang
2013 J jnl
Reactant and Waste Minimization in Multitarget Sample Preparation on Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Juinn-Dar Huang, Chia-Hung Liu, Huei-Shan Lin
2013 A conf
Sample preparation for many-reactant bioassay on DMFBs using common dilution operation sharing.
ICCAD
Chia-Hung Liu, Hao-Han Chang, Tung-Che Liang, Juinn-Dar Huang
2013 — conf
Tutorial: Digital microfluidic biochips: Towards hardware/software co-design and cyber-physical system integration.
SoCC
Tsung-Yi Ho, Juinn-Dar Huang, Paul Pop
2012 J jnl
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Juinn-Dar Huang, Chia-I Chen, Wan-Ling Hsu, Yen-Ting Lin, Jing-Yang Jou
2012 A conf
Reactant minimization during sample preparation on digital microfluidic biochips using skewed mixing trees.
ICCAD
Juinn-Dar Huang, Chia-Hung Liu, Ting-Wei Chiang
2012 A conf
Thermal-aware logic block placement for 3D FPGAs considering lateral heat dissipation (abstract only).
FPGA
Juinn-Dar Huang, Ya-Shih Huang, Mi-Yu Hsu, Han-Yuan Chang
2011 — conf
Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family.
ISVLSI
Chia-I Chen, Juinn-Dar Huang
2011 A conf
Architectural exploration of 3D FPGAs towards a better balance between area and delay.
DATE
Chia-I Chen, Bau-Cheng Lee, Juinn-Dar Huang
2011 J jnl
Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Juinn-Dar Huang, Chia-I Chen, Yen-Ting Lin, Wan-Ling Hsu
2011 — conf
Equivalence checking of scheduling with speculative code transformations in high-level synthesis.
ASP-DAC
Chi-Hui Lee, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou
2011 — conf
Layer-Aware Design Partitioning for Vertical Interconnect Minimization.
ISVLSI
Ya-Shih Huang, Yang-Hsiang Liu, Juinn-Dar Huang
2011 — conf
Throughput optimization for latency-insensitive system with minimal queue insertion.
ASP-DAC
Juinn-Dar Huang, Yi-Hang Chen, Ya-Chien Ho
2010 J jnl
A Hierarchical Criticality-Aware Architectural Synthesis Framework for Multicycle Communication.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Chia-I Chen, Juinn-Dar Huang
2010 — conf
Expandable MDC-based FFT architecture and its generator for high-performance applications.
SoCC
Bu-Ching Lin, Yu-Hsiang Wang, Juinn-Dar Huang, Jing-Yang Jou
2010 J jnl
FSM-Based Formal Compliance Verification of Interface Protocols.
J. Inf. Sci. Eng.
Che-Hua Shih, Ya-Ching Yang, Chia-Chih Yen, Juinn-Dar Huang, Jing-Yang Jou
2009 J jnl
Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM.
IEEE Trans. Very Large Scale Integr. Syst.
Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou
2009 J jnl
Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Ya-Shih Huang, Yu-Ju Hong, Juinn-Dar Huang
2009 — conf
CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture.
ASP-DAC
Chia-I Chen, Juinn-Dar Huang
2009 J jnl
Reducing fault dictionary size for million-gate large circuits.
ACM Trans. Design Autom. Electr. Syst.
Yu-Ru Hong, Juinn-Dar Huang
2009 — conf
Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture.
ASP-DAC
Yu-Ju Hong, Ya-Shih Huang, Juinn-Dar Huang
2008 — ed.
2008 International Conference on Field-Programmable Technology, FPT 2008, Taipei, Taiwan, December 7-10, 2008
FPT
Tarek A. El-Ghazawi, Yao-Wen Chang, Juinn-Dar Huang, Proshanta Saha
2008 — conf
A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing.
ASP-DAC
Wei-Sheng Huang, Yu-Ru Hong, Juinn-Dar Huang, Ya-Shih Huang
2008 — conf
Cycle-time-aware sequential way-access set-associative cache for low energy consumption.
APCCAS
Chih-Hui Ting, Juinn-Dar Huang, Yu-Hsiang Kao
2008 — conf
Low power multiplexer tree design using dynamic propagation path control.
APCCAS
Nan-Shing Li, Juinn-Dar Huang, Han-Jung Huang
2008 J jnl
Verification of Pin-Accurate Port Connections.
IEEE Des. Test Comput.
Geeng-Wei Lee, Juinn-Dar Huang, Chun-Yao Wang, Jing-Yang Jou
2007 — conf
A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses.
ASP-DAC
Bu-Ching Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou
2007 — conf
Fault Dictionary Size Reduction for Million-Gate Large Circuits.
ASP-DAC
Yu-Ru Hong, Juinn-Dar Huang
2006 — conf
A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication.
ASP-DAC
Chien-Hua Chen, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou
2006 — conf
FSM-based transaction-level functional coverage for interface compliance verification.
ASP-DAC
Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou
2005 — conf
Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model.
HLDVT
Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou
2004 A conf
Verification on Port Connections.
ITC
Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang
2001 J jnl
Unified functional decomposition via encoding for FPGA technology mapping.
IEEE Trans. Very Large Scale Integr. Syst.
Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang
2000 J jnl
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping.
IEEE Trans. Very Large Scale Integr. Syst.
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
1998 A* conf
Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis.
DAC
Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang
1998 J jnl
On circuit clustering for area/delay tradeoff under capacity and pin constraints.
IEEE Trans. Very Large Scale Integr. Syst.
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang
1997 — conf
BDD based lambda set selection in Roth-Karp decomposition for LUT architecture.
ASP-DAC
Jie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang, Jung-Shian Wei
1996 A conf
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping.
ICCAD
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
1995 A conf
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture.
ICCAD
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
1995 A* conf
Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping.
DAC
Wen-Zen Shen, Juinn-Dar Huang, Shih-Min Chao