Juin-Ming Lu - RankMe

27 papers A* 1A 4B 1C 2Journal 4Unranked 15

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Low-Complexity and Reconfigurable Design for Nonlinear Function Approximation in Transformers. IEEE Trans. Circuits Syst. II Express Briefs Qi-Xian Wu, Shu-Sian Teng, Ming-Der Shieh, Chih-Tsun Huang, Juin-Ming Lu
2025	C	`conf`	A Low-complexity and Reconfigurable Design for Nonlinear Function Approximation in Transformers. ISCAS Qi-Xian Wu, Shu-Sian Teng, Ming-Der Shieh, Chih-Tsun Huang, Juin-Ming Lu
2025	—	`conf`	An Adaptive Scheme of Threshold Adjustment for Dynamic Sparsity Extraction of Self-Attention Network. AICAS Yong-Lun Xiao, Chia-Wei Chang, Cheng-Ting Shih, Jing-Jia Liou, Chih-Tsun Huang, Yao-Hua Chen, Juin-Ming Lu
2025	—	`conf`	Enhancing Semi-Supervised Learners via Similarity-Based Self-Supervised Models. NewCAS ShengPo Lin, Hsiang-Cheng Hsieh, Lianzheng Lin, Kuei-Chung Chang, Juin-Ming Lu, Tay-Jyi Lin, Tien-Fu Chen
2025	—	`conf`	Hybrid Bayesian Optimization with Early Termination Strategies for Auto Tuning. ISVLSI Hsiang-Cheng Hsieh, ShengPo Lin, Arbind Kumar Mahto, Kuei-Chung Chang, Juin-Ming Lu, Tay-Jyi Lin, Tien-Fu Chen
2024	—	`conf`	Efficient Inference of Transformers on Bare-Metal Devices with RISC-V Vector Processors. NewCAS Yi-Xuan Huang, Po-Han Huang, Juin-Ming Lu, Tay-Jyi Lin, Tien-Fu Chen
2023	—	`conf`	HierArch: A Cluster-Based DNN Accelerator with Hierarchical Buses for Design Space Exploration. SOCC Jyun-Siou Huang, Ting-Han Chou, Juin-Ming Lu, Chih-Tsun Huang, Jing-Jia Liou
2023	C	`conf`	MultiFuse: Efficient Cross Layer Fusion for DNN Accelerators with Multi-level Memory Hierarchy. ICCD Chia-Wei Chang, Jing-Jia Liou, Chih-Tsun Huang, Wei-Chung Hsu, Juin-Ming Lu
2023	—	`conf`	Optimization of AI SoC with Compiler-assisted Virtual Design Platform. ISPD Chih-Tsun Huang, Juin-Ming Lu, Yao-Hua Chen, Ming-Chih Tung, Shih-Chieh Chang
2022	—	`conf`	Efficient Segment-wise Pruning for DCNN Inference Accelerators. VLSI-DAT Che-Chang Yang, Yung-Tai Shih, Chun-Chen Chen, Chih-Tsun Huang, Jing-Jia Liou, Yao-Hua Chen, Juin-Ming Lu
2022	A	`conf`	Fault Modeling and Testing of Memristor-Based Spiking Neural Networks. ITC Kuan-Wei Hou, Hsueh-Hung Cheng, Chi Tung, Cheng-Wen Wu, Juin-Ming Lu
2021	A	`conf`	An Improved STBP for Training High-Accuracy and Low-Spike-Count Spiking Neural Networks. DATE Pai-Yu Tan, Cheng-Wen Wu, Juin-Ming Lu
2021	J	`jnl`	Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation. IEEE Trans. Very Large Scale Integr. Syst. Jai-Ming Lin, Tai-Ting Chen, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu
2021	J	`jnl`	Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC. IEEE Trans. Very Large Scale Integr. Syst. Jai-Ming Lin, Wei-Yi Chang, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu
2021	—	`conf`	Tile-Based Architecture Exploration for Convolutional Accelerators in Deep Neural Networks. AICAS Yang-Tsai Chen, Yu-Xiang Yen, Chun-Tse Chen, Tzu-yu Chen, Chih-Tsun Huang, Jing-Jia Liou, Juin-Ming Lu
2020	A*	`conf`	A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification. DAC Po-Yao Chuang, Pai-Yu Tan, Cheng-Wen Wu, Juin-Ming Lu
2020	J	`jnl`	A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification. CoRR Pai-Yu Tan, Po-Yao Chuang, Yen-Ting Lin, Cheng-Wen Wu, Juin-Ming Lu
2019	—	`conf`	NNSim: A Fast and Accurate SystemC/TLM Simulator for Deep Convolutional Neural Network Accelerators. VLSI-DAT Yi-Che Lee, Ting-Shuo Hsu, Chun-Tse Chen, Jing-Jia Liou, Juin-Ming Lu
2018	A	`conf`	A fast thermal-aware fixed-outline floorplanning methodology based on analytical models. ICCAD Jai-Ming Lin, Tai-Ting Chen, Yen-Fu Chang, Wei-Yi Chang, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu
2018	—	`conf`	Fast Steady-State Thermal Analysis. ISOCC Lih-Yih Chiou, Chun-Hao Chang, Liang-Ying Lu, Wei-Hsuan Yang, Yeong-Jar Chang, Juin-Ming Lu
2018	B	`conf`	Full System Emulation of Embedded Heterogeneous Multicores Based on QEMU. ICPADS I-Hua Chen, Chung-Ta King, Yao-Hua Chen, Juin-Ming Lu
2017	—	`conf`	Application specific component-service-aware trace generation on Android-QEMU. SoCC Hao-Lun Wei, Chung-Ta King, Bhaskar Das, Mei-Chiao Peng, Chen-Chieh Wang, Hsun-Lun Huang, Juin-Ming Lu
2017	—	`conf`	Content-aware line-based power modeling methodology for image signal processor. SoCC Chun-Wei Chen, Ming-Der Shieh, Juin-Ming Lu, Hsun-Lun Huang, Yao-Hua Chen
2017	—	`conf`	Design space exploration with a cycle-accurate systemC/TLM DRAM controller model. VLSI-DAT Ting-Shuo Hsu, Chao-Chieh Wu, Che-Wei Hsu, Chih-Tsun Huang, Jing-Jia Liou, Yao-Hua Chen, Juin-Ming Lu
2014	—	`conf`	Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications. SoCC Jyu-Yuan Lai, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou, Tung-Hua Yeh, Liang-Chia Cheng, Juin-Ming Lu
2014	—	`conf`	Reconfigurable Network-on-chip design for heterogeneous multi-core system architecture. HPCS Jih-Sheng Shen, Pao-Ann Hsiung, Juin-Ming Lu
2000	A	`conf`	Cost and Benefit Models for Logic and Memory BIST. DATE Juin-Ming Lu, Cheng-Wen Wu