Jui-Jen Wu

18 papers C 1Journal 11Unranked 6
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device.
IEEE J. Solid State Circuits
Jen-Chun Tien, Ping-Chun Wu, Win-San Khwa, Ashwin Sanjay Lele, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2025 — conf
14.2 A 16nm 216kb, 188.4TOPS/W and 133.5TFLOPS/W Microscaling Multi-Mode Gain-Cell CIM Macro Edge-AI Devices.
ISSCC
Win-San Khwa, Ping-Chun Wu, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Ashwin Sanjay Lele, Jui-Jen Wu, Jen-Chun Tien, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2025 C conf
A 16.42 TOPS/mm
ISCAS
Tsung-Han Wu, Yu-Tse Shih, Hsin-Yung Fu, Chia Ling Ho, Wai-Chi Fang, Ke-Horng Chen, Kuo-Lin Zheng, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai, Jui-Jen Wu, Meng-Fan Marvin Chang
2025 J jnl
An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips.
IEEE J. Solid State Circuits
Ping-Chun Wu, Win-San Khwa, Jui-Jen Wu, Jian-Wei Su, Chuan-Jia Jhang, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2024 — conf
34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices.
ISSCC
Win-San Khwa, Ping-Chun Wu, Jui-Jen Wu, Jian-Wei Su, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2024 J jnl
A 22 nm 10.03-237.99 TOPS/W Time-Digital-Hybrid SRAM Compute-in-Memory AI Accelerator for GNN Edge Device Applications.
IEEE Trans. Circuits Syst. Artif. Intell.
Chuan-Jia Jhang, Win-San Khwa, Ping-Chun Wu, Ashwin Sanjay Lele, Ping-Sheng Wu, Chao-En Ke, Ting-Chien Chiu, Yu-Cheng Hung, Wei-Ting Hsu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Jui-Jen Wu, Meng-Fan Chang
2024 — conf
A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro.
VLSI Technology and Circuits
De-Qi You, Win-San Khwa, Jui-Jen Wu, Chuan-Jia Jhang, Guan-Yi Lin, Po-Jung Chen, Ting-Chien Chiu, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2023 — conf
A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices.
VLSI Technology and Circuits
Tai-Hao Wen, Je-Min Hung, Hung-Hsi Hsu, Yuan Wu, Fu-Chun Chang, Chung-Yuan Li, Chih-Han Chien, Chin-I Su, Win-San Khwa, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Mon-Shu Ho, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang
2015 J jnl
An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros.
IEEE J. Solid State Circuits
Meng-Fan Chang, Yu-Fan Lin, Yen-Chen Liu, Jui-Jen Wu, Shin-Jang Shen, Wu-Chin Tsai, Yu-Der Chih
2015 J jnl
Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations.
IEEE J. Solid State Circuits
Meng-Fan Chang, Jui-Jen Wu, Tun-Fei Chien, Yen-Chen Liu, Ting-Chin Yang, Wen-Chao Shen, Ya-Chin King, Chrong Jung Lin, Ku-Feng Lin, Yu-Der Chih, Tsung-Yung Jonathan Chang
2014 — conf
19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme.
ISSCC
Meng-Fan Chang, Jui-Jen Wu, Tun-Fei Chien, Yen-Chen Liu, Ting-Chin Yang, Wen-Chao Shen, Ya-Chin King, Chorng-Jung Lin, Ku-Feng Lin, Yu-Der Chih, Sreedhar Natarajan, Tsung-Yung Jonathan Chang
2014 J jnl
Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme.
IEEE J. Solid State Circuits
Meng-Fan Chang, Chia-Chen Kuo, Shyh-Shyuan Sheu, Chorng-Jung Lin, Ya-Chin King, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Jui-Jen Wu, Yu-Der Chih
2013 J jnl
A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V
IEEE J. Solid State Circuits
Meng-Fan Chang, Ming-Bin Chen, Lai-Fu Chen, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Hsiu-Yun Su, Yuan-Hua Chu, Wen-Chin Wu, Tzu-Yi Yang, Hiroyuki Yamauchi
2012 — conf
A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques.
VLSIC
Ming-Pin Chen, Lai-Fu Chen, Meng-Fan Chang, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Mon-Shu Ho, Hsiu-Yun Su, Yuan-Hua Chu, Wen-Chin Wu, Tzu-Yi Yang, Hiroyuki Yamauchi
2012 J jnl
A 45-nm Dual-Port SRAM Utilizing Write-Assist Cells Against Simultaneous Access Disturbances.
IEEE Trans. Circuits Syst. II Express Briefs
Jui-Jen Wu, Meng-Fan Chang, Shau-Wei Lu, Robert Lo, Quincy Li
2011 J jnl
A Large Sigma V
IEEE J. Solid State Circuits
Jui-Jen Wu, Yen-Hui Chen, Meng-Fan Chang, Po-Wei Chou, Chien-Yuan Chen, Hung-Jen Liao, Ming-Bin Chen, Yuan-Hua Chu, Wen-Chin Wu, Hiroyuki Yamauchi
2010 J jnl
A Differential Data-Aware Power-Supplied (D
IEEE J. Solid State Circuits
Meng-Fan Chang, Jui-Jen Wu, Kuang-Ting Chen, Yung-Chi Chen, Yen-Hui Chen, Robin Lee, Hung-Jen Liao, Hiroyuki Yamauchi
2009 J jnl
A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs.
IEEE J. Solid State Circuits
Yen-Huei Chen, Gary Chan, Shao-Yu Chou, Hsien-Yu Pan, Jui-Jen Wu, Robin Lee, Hung-Jen Liao, Hiroyuki Yamauchi