Jue-Hsien Chern

11 papers A* 1A 4C 1Journal 4Unranked 1
YearRankTypeTitle / Venue / Authors
2006 A* conf
Tomorrow's analog: just dead or just different?
DAC
Shekhar Borkar, Robert W. Brodersen, Jue-Hsien Chern, Eric Naviasky, D. Saias, Charles G. Sodini
2005 — conf
Challenges of analog/mixed-signal SoC design and verification.
ISPD
Jue-Hsien Chern
1993 J jnl
Algorithms for transient three-dimensional mixed-level circuit and device simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kartikeya Mayaram, Jue-Hsien Chern, Ping Yang
1993 A conf
An accurate grid local truncation error for device simulation.
ICCAD
Mi-Chang Chang, Jue-Hsien Chern, Ping Yang
1993 J jnl
Design for reliability: the major challenge for VLSI.
Proc. IEEE
Ping Yang, Jue-Hsien Chern
1993 C conf
Efficient and Robust Path Tracing Algorithm for DC Convergence Problem.
ISCAS
Mi-Chang Chang, Jue-Hsien Chern, Ping Yang
1991 A conf
Transient Three-Dimensional Mixed-Level Circuit and Device Simulation: Algorithms and Applications.
ICCAD
Kartikeya Mayaram, Ping Yang, Jue-Hsien Chern
1990 A conf
A Parallel Block-Diagonal Preconditioned Conjugate-Gradient Solution Algorithm for Circuit and Device Simulations.
ICCAD
Kartikeya Mayaram, Ping Yang, Jue-Hsien Chern, Richard Burch, Lawrence A. Arledge Jr., Paul F. Cox
1989 A conf
PGS and PLUCGS-two new matrix solution techniques for general circuit simulation.
ICCAD
Richard Burch, Kartikeya Mayaram, Jue-Hsien Chern, Ping Yang, Paul F. Cox
1989 J jnl
SIERRA: a 3-D device simulator for reliability modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jue-Hsien Chern, John T. Maeda, Lawrence A. Arledge Jr., Ping Yang
1987 J jnl
A Predictor/CAD Model for Buried-Channel MOS Transistors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
K. C.-K. Weng, Ping Yang, Jue-Hsien Chern