Judit Freijedo

16 papers B 2C 4Journal 5Unranked 5
YearRankTypeTitle / Venue / Authors
2013 B conf
Aging monitoring with local sensors in FPGA-based designs.
FPL
Carlos Leong, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira, María Dolores Valdés, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas
2012 J jnl
Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits.
J. Electron. Test.
Judit Freijedo, Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira
2011 J jnl
Lower
J. Low Power Electron.
Judit Freijedo, María Dolores Valdés, Lucía Costas, María José Moure, Juan J. Rodríguez-Andina, Jorge Semião, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira
2011 — conf
Modeling the effect of process variations on the timing response of nanometer digital circuits.
LATW
Judit Freijedo, Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira
2011 B conf
Performance Failure Prediction Using Built-In Delay Sensors in FPGAs.
FPL
Vasco Bexiga, Carlos Leong, Jorge Semião, Isabel C. Teixeira, João Paulo Teixeira, María Dolores Valdés, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas
2011 — conf
Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects.
LATW
María Dolores Valdés, Judit Freijedo, María José Moure, Juan J. Rodríguez-Andina, Jorge Semião, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira
2010 J jnl
Impact of Power Supply Voltage Variations on FPGA-Based Digital Systems Performance.
J. Low Power Electron.
Judit Freijedo, Lucía Costas, Jorge Semião, Juan J. Rodríguez-Andina, María José Moure, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira
2009 C conf
Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies.
IOLTS
Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2009 — conf
Measuring clock-signal modulation efficiency for Systems-on-Chip in electromagnetic interference environment.
LATW
Jorge Semião, Judit Freijedo, Marlon Moraes, M. Mallmann, Carlos Lemos Antunes, Juliano Benfica, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, Juan J. Rodríguez-Andina, João Paulo Teixeira, Daniel Lupi, Edmundo Gatti, Luis Garcia, Fernando Hernandez
2008 J jnl
Delay Modeling for Power Noise and Temperature-Aware Design and Test of Digital Systems.
J. Low Power Electron.
Judit Freijedo, Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira
2008 C conf
Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits.
IOLTS
Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2008 — conf
Robust solution for synchronous communication among multi clock domains.
APCCAS
Jorge Semião, João Varela, Judit Freijedo, Juan J. Rodríguez-Andina, Carlos Leong, João Paulo Teixeira, Isabel C. Teixeira
2008 J jnl
Time Management for Low-Power Design of Digital Systems.
J. Low Power Electron.
Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2007 — conf
Enhancing the Tolerance to Power-Supply Instability in Digital Circuits.
ISVLSI
Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2007 C conf
Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits.
DDECS
Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2007 C conf
On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits.
IOLTS
Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira