Jude Haris

11 papers A 1B 1C 1Journal 8
YearRankTypeTitle / Venue / Authors
2025 B conf
Accelerating Transposed Convolutions on FPGA-Based Edge Devices.
FPL
Jude Haris, José Cano
2025 J jnl
Accelerating Transposed Convolutions on FPGA-based Edge Devices.
CoRR
Jude Haris, José Cano
2025 J jnl
F-BFQ: Flexible Block Floating-Point Quantization Accelerator for LLMs.
CoRR
Jude Haris, José Cano
2024 A conf
AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators.
CGO
Nicolas Bohm Agostini, Jude Haris, Perry Gibson, Malith Jayaweera, Norm Rubin, Antonino Tumeo, José L. Abellán, José Cano, David R. Kaeli
2024 J jnl
Accelerating PoT Quantization on Edge Devices.
CoRR
Rappy Saha, Jude Haris, José Cano
2024 J jnl
Data Transfer Optimizations for Host-CPU and Accelerators in AXI4MLIR.
CoRR
Jude Haris, Nicolas Bohm Agostini, Antonino Tumeo, David R. Kaeli, José Cano
2024 J jnl
Designing Efficient LLM Accelerators for Edge Devices.
CoRR
Jude Haris, Rappy Saha, Wenhao Hu, José Cano
2023 J jnl
AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators.
CoRR
Nicolas Bohm Agostini, Jude Haris, Perry Gibson, Malith Jayaweera, Norm Rubin, Antonino Tumeo, José L. Abellán, José Cano, David R. Kaeli
2023 J jnl
SECDA-TFLite: A toolkit for efficient development of FPGA-based DNN accelerators for edge inference.
J. Parallel Distributed Comput.
Jude Haris, Perry Gibson, José Cano, Nicolas Bohm Agostini, David R. Kaeli
2021 C conf
SECDA: Efficient Hardware/Software Co-Design of FPGA-based DNN Accelerators for Edge Inference.
SBAC-PAD
Jude Haris, Perry Gibson, José Cano, Nicolas Bohm Agostini, David R. Kaeli
2021 J jnl
SECDA: Efficient Hardware/Software Co-Design of FPGA-based DNN Accelerators for Edge Inference.
CoRR
Jude Haris, Perry Gibson, José Cano, Nicolas Bohm Agostini, David R. Kaeli