Juanjo Noguera

38 papers A* 1A 4B 6C 2Misc 3Journal 9Unranked 13

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	AMD XDNA NPU in Ryzen AI Processors. IEEE Micro Alejandro Rico, Satyaprakash Pareek, Javier Cabezas, David Clarke, Baris Özgül, Francisco Barat, Yao Fu, Stephan Münz, Dylan Stuart, Patrick Schlangen, Pedro Duarte, Sneha Date, Indrani Paul, Jian Weng, Sonal Santan, Vinod Kathail, Ashish Sirasao, Juanjo Noguera
2019	—	`conf`	Xilinx First 7nm Device: Versal AI Core (VC1902). Hot Chips Symposium Sagheer Ahmad, Sridhar Subramanian, Vamsi Boppana, Shankar Lakka, Fu-Hing Ho, Tomai Knopp, Juanjo Noguera, Gaurav Singh, Ralph Wittig
2015	J	`jnl`	Coarse-Grain Performance Estimator for Heterogeneous Parallel Computing Architectures like Zynq All-Programmable SoC. CoRR Daniel Jiménez-González, Carlos Álvarez, Antonio Filgueras, Xavier Martorell, Jan Langer, Juanjo Noguera, Kees A. Vissers
2014	A	`conf`	OmpSs@Zynq all-programmable SoC ecosystem. FPGA Antonio Filgueras, Eduard Gil, Daniel Jiménez-González, Carlos Álvarez, Xavier Martorell, Jan Langer, Juanjo Noguera, Kees A. Vissers
2013	C	`conf`	Heterogeneous tasking on SMP/FPGA SoCs: The case of OmpSs and the Zynq. VLSI-SoC Antonio Filgueras, Eduard Gil, Carlos Álvarez, Daniel Jiménez-González, Xavier Martorell, Jan Langer, Juanjo Noguera
2013	C	`conf`	Software-programmable digital pre-distortion on the Zynq SoC. VLSI-SoC Baris Özgül, Jan Langer, Juanjo Noguera, Kees A. Vissers
2011	J	`jnl`	A Model-Based Approach to Cognitive Radio Design. IEEE J. Sel. Areas Commun. Jorg Lotze, Suhaib A. Fahmy, Juanjo Noguera, Linda Doyle
2011	A	`conf`	Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools. DATE Kees A. Vissers, Stephen Neuendorffer, Juanjo Noguera
2011	B	`conf`	Embedded Systems Start-Up under Timing Constraints on Modern FPGAs. FPL Joachim Meyer, Juanjo Noguera, Michael Hübner, Rodney Stewart, Jürgen Becker
2011	A	`conf`	Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration. DATE Joachim Meyer, Juanjo Noguera, Michael Hübner, Lars Braun, Oliver Sander, R. M. Gil, Rodney Stewart, Jürgen Becker
2011	J	`jnl`	High-Level Synthesis for FPGAs: From Prototyping to Deployment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo Noguera, Kees A. Vissers, Zhiru Zhang
2010	J	`jnl`	Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures. ACM Trans. Reconfigurable Technol. Syst. Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil D. Dutt
2010	—	`conf`	FPGA Startup Through Sequential Partial and Dynamic Reconfiguration. ISVLSI (Selected papers) Joachim Meyer, Michael Hübner, Lars Braun, Oliver Sander, Juanjo Noguera, Rodney Stewart, Jürgen Becker
2010	—	`conf`	Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration. ISVLSI Michael Hübner, Joachim Meyer, Oliver Sander, Lars Braun, Jürgen Becker, Juanjo Noguera, Rodney Stewart
2010	—	`conf`	Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs. IPDPS Workshops Michael Hübner, Diana Göhringer, Juanjo Noguera, Jürgen Becker
2010	J	`jnl`	Iris: an architecture for cognitive radio networking testbeds. IEEE Commun. Mag. Paul D. Sutton, Jörg Lotze, Hicham Lahlou, Suhaib A. Fahmy, Keith E. Nolan, Baris Özgül, Thomas W. Rondeau, Juanjo Noguera, Linda Doyle
2010	—	`conf`	Multi-platform demonstrations using the Iris architecture for cognitive radio network testbeds. CrownCom Paul D. Sutton, Jörg Lotze, Hicham Lahlou, Baris Özgül, Suhaib A. Fahmy, Keith E. Nolan, Juanjo Noguera, Linda E. Doyle
2009	B	`conf`	Development Framework for Implementing FPGA-Based Cognitive Network Nodes. GLOBECOM Jorg Lotze, Suhaib A. Fahmy, Juanjo Noguera, Baris Özgül, Linda Doyle, Robert Esser
2009	Misc	`conf`	Generic Software Framework for Adaptive Applications on FPGAs. FCCM Suhaib A. Fahmy, Jorg Lotze, Juanjo Noguera, Linda Doyle, Robert Esser
2008	—	`conf`	Towards Novel Approaches in Design Automation for FPGA Power Optimization. PATMOS Juanjo Noguera, Robert Esser, Katarina Paulsson, Michael Hübner, Jürgen Becker
2007	B	`conf`	Power Reduction in Network Equipment through Adaptive Partial Reconfiguration. FPL Juanjo Noguera, Irwin O. Kennedy
2007	A*	`conf`	Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures. DAC Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt, Juanjo Noguera
2006	—	`conf`	Minimizing peak power for application chains on architectures with partial dynamic reconfiguration. FPT Sudarshan Banerjee, Elaheh Bozorgzadeh, Juanjo Noguera, Nikil D. Dutt
2006	—	`conf`	Software-friendly HW/SW co-simulation: an industrial case study. DATE Designers' Forum Juanjo Noguera, Luis Baldez, Narcis Simon, Lluis Abello
2006	J	`jnl`	System-level power-performance tradeoffs for reconfigurable computing. IEEE Trans. Very Large Scale Integr. Syst. Juanjo Noguera, Rosa M. Badia
2005	—	`conf`	Improved Microarchitecture Support for Dynamic Task Scheduling on Reconfigurable Architectures. ERSA Zexin Pan, Juanjo Noguera, B. Earl Wells
2005	B	`conf`	Performance and Energy Analysis of Task-Level Graph Transformation Techniques for Dynamically Reconfigurable Architectures. FPL Juanjo Noguera, Rosa M. Badia
2004	J	`jnl`	Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling. ACM Trans. Embed. Comput. Syst. Juanjo Noguera, Rosa M. Badia
2004	Misc	`conf`	Power-performance trade-offs for reconfigurable computing. CODES+ISSS Juanjo Noguera, Rosa M. Badia
2003	Misc	`conf`	System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures. CASES Juanjo Noguera, Rosa M. Badia
2002	—	`conf`	Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures. CODES Juanjo Noguera, Rosa M. Badia
2002	J	`jnl`	HW/SW codesign techniques for dynamically reconfigurable architectures. IEEE Trans. Very Large Scale Integr. Syst. Juanjo Noguera, Rosa M. Badia
2001	A	`conf`	A HW/SW partitioning algorithm for dynamically reconfigurable architectures. DATE Juanjo Noguera, Rosa M. Badia
2000	B	`conf`	Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers. FPL Juanjo Noguera, Rosa M. Badia
2000	—	`conf`	Modelling and Performance Evaluation of a National Scale Switchless Based Network. INTERWORKING Josep Solé-Pareta, Davide Careglio, Salvatore Spadaro, Jaume Masip-Torné, Juanjo Noguera, Gabriel Junyent
2000	—	`conf`	Run-Time HW/SW Codesign for Discrete Event Systems using Dynamically Reconfigurable Architectures. ISSS Juanjo Noguera, Rosa M. Badia
1999	B	`conf`	A HW/SW Codesign-Based Reconfigurable Environment for Telecommunication Network Simulation. FPL Juanjo Noguera, Rosa M. Badia, Jordi Domingo-Pascual, Josep Solé-Pareta
1999	—	`conf`	Reconfigurable Computing: An Innovative Solution for Multimedia and Telecommunication Networks Simulation. EUROMICRO Juanjo Noguera, Rosa M. Badia, Jordi Domingo-Pascual, Josep Solé-Pareta