Juan Valverde

14 papers A* 1B 1C 1Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2025 J jnl
Reducing the gap between general purpose data and aerial images in concentrated solar power plants.
CoRR
Miguel Angel Pérez-Cutiño, Juan Valverde, Jesús Capitán, José Miguel Díaz-Báñez
2024 A* conf
Measuring Ball Joint Faults in Parabolic-Trough Solar Plants with Data Augmentation and Deep Learning.
ICRA
Miguel Angel Pérez-Cutiño, Jesús Capitán, José Miguel Díaz-Báñez, Juan Valverde
2024 J jnl
Optimal energy collection with rotational movements constraints in concentrated solar power plants.
CoRR
José Miguel Díaz-Báñez, José-Manuel Higes-López, Miguel Angel Pérez-Cutiño, Juan Valverde
2019 — conf
A Fast Prototyping Workflow for Reconfigurable SDR Applications.
ReCoSoC
Alejandro G. Gener, Juan Valverde, J. Andrés Otero, Philip J. Harris
2018 J jnl
FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo
Sensors
Alfonso Rodríguez, Juan Valverde, Jorge Portilla, Andrés Otero, Teresa Riesgo, Eduardo de la Torre
2015 — conf
Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs.
ReConFig
Alfonso Rodríguez, Juan Valverde, Eduardo de la Torre
2015 — conf
Execution modeling in self-aware FPGA-based architectures for efficient resource management.
ReCoSoC
Alfonso Rodríguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2015 C conf
Live demonstration: A dynamically adaptable image processing application running in an FPGA-based WSN platform.
ISCAS
Alfonso Rodríguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2014 B conf
A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems.
FPL
Juan Valverde, Alfonso Rodríguez, Julio Camarero, Andrés Otero, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2014 — conf
Dynamic management of multikernel multithread accelerators using Dynamic Partial Reconfiguration.
ReCoSoC
Alfonso Rodríguez, Juan Valverde, Eduardo de la Torre, Teresa Riesgo
2014 — conf
Power-aware multi-objective evolvable hardware system on an FPGA.
AHS
Blanca López, Juan Valverde, Eduardo de la Torre, Teresa Riesgo
2012 — conf
Power management techniques in an FPGA-based WSN node for high performance applications.
ReCoSoC
Miguel Lombardo, Julio Camarero, Juan Valverde, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2012 J jnl
Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks.
Sensors
Juan Valverde, Andrés Otero, Miguel Lopez, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2012 J jnl
Wireless Sensor Network for Environmental Monitoring: Application in a Coffee Factory.
Int. J. Distributed Sens. Networks
Juan Valverde, Victor Rosello, Gabriel Mujica, Jorge Portilla, Amaia Uriarte, Teresa Riesgo