Juan Núñez - RankMe

45 papers C 8Journal 12Unranked 25

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Exploring Charge-Based Mosfet Compact Models with ACM-2 as a Design-Oriented Paradigm. LASCAS Rafaella Fiorelli, Matías R. Miguez, Juan Núñez
2023	—	`conf`	Characterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic Paths. IRPS Victor M. van Santen, Jose M. Gata-Romero, Juan Núñez, Rafael Castro-López, Elisenda Roca, Hussam Amrouch
2023	—	`conf`	Exploitation of Subharmonic Injection Locking for Solving Combinatorial Optimization Problems with Coupled Oscillators using VO2 based devices. SMACD Juan Núñez, Maria J. Avedillo, Manuel Jiménez Través
2023	J	`jnl`	Operating Coupled VO₂-Based Oscillators for Solving Ising Models. IEEE J. Emerg. Sel. Topics Circuits Syst. Maria J. Avedillo, Manuel Jiménez Través, Corentin Delacour, Aida Todri-Sanial, Bernabé Linares-Barranco, Juan Núñez
2023	—	`conf`	Reliability evaluation of IC Ring Oscillator PUFs. SMACD Jose M. Gata-Romero, Elisenda Roca, Juan Núñez, Rafael Castro-López, Francisco V. Fernández
2022	—	`conf`	Enhancing Storage Capabilities of Oscillatory Neural Networks as Associative Memory. DCIS Manuel Jiménez Través, Maria José Avedillo, Juan Núñez, Bernabé Linares-Barranco
2022	J	`jnl`	Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs. IEEE Embed. Syst. Lett. Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio J. Acosta
2022	J	`jnl`	How Frequency Injection Locking Can Train Oscillatory Neural Networks to Compute in Phase. IEEE Trans. Neural Networks Learn. Syst. Aida Todri-Sanial, Stefania Carapezzi, Corentin Delacour, Madeleine Abernot, Thierry Gil, Elisabetta Corti, Siegfried F. Karg, Juan Núñez, Manuel Jiménez Través, Maria J. Avedillo, Bernabé Linares-Barranco
2022	—	`conf`	Mitigating the Impact of Variability in NCFET-based Coupled-Oscillator Networks Applications. ICECS 2022 Juan Núñez, Simon Thomann, Hussam Amrouch, Maria J. Avedillo
2021	J	`jnl`	Design and Analysis of Secure Emerging Crypto-Hardware Using HyperFET Devices. IEEE Trans. Emerg. Top. Comput. Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio J. Acosta
2021	J	`jnl`	Insights Into the Dynamics of Coupled VO IEEE Trans. Circuits Syst. II Express Briefs Juan Núñez, José M. Quintana, Maria José Avedillo, Manuel Jiménez Través, Aida Todri-Sanial, Elisabetta Corti, Siegfried F. Karg, Bernabé Linares-Barranco
2020	C	`conf`	An Approach to the Device-Circuit Co-Design of HyperFET Circuits. ISCAS Manuel Jiménez Través, Juan Núñez, Maria José Avedillo
2020	J	`jnl`	Projection of Dual-Rail DPA Countermeasures in Future FinFET and Emerging TFET Technologies. ACM J. Emerg. Technol. Comput. Syst. Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio J. Acosta
2019	—	`conf`	An IC Array for the Statistical Characterization of Time-Dependent Variability of Basic Circuit Blocks. SMACD Pablo Martín-Lloret, Juan Núñez, Elisenda Roca, Rafael Castro-López, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2019	J	`jnl`	Emerging technologies and computing paradigms for the Internet of Everything applications. International Journal of Circuit, Theory, and Applications. Int. J. Circuit Theory Appl. Aida Todri-Sanial, Xueqing Li, Juan Núñez
2019	—	`conf`	Experimental Characterization of Time-Dependent Variability in Ring Oscillators. SMACD Juan Núñez, Elisenda Roca, Rafael Castro-López, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2019	J	`jnl`	Power and Speed Evaluation of Hyper-FET Circuits. IEEE Access Juan Núñez, Maria J. Avedillo
2018	—	`conf`	All-inversion region gm/ID methodology for RF circuits in FinFET technologies. NEWCAS Rafaella Fiorelli, Juan Núñez, Fernando Silveira
2018	—	`conf`	Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits. DCIS Erica Tena-Sánchez, Ignacio M. Delgado-Lozano, Juan Núñez, Antonio J. Acosta
2018	—	`conf`	Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models. SMACD Pablo Saraza-Canflanca, D. Malagon, Fábio Passos, A. Toro, Juan Núñez, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2018	J	`jnl`	Impact of the RT-level architecture on the power performance of tunnel transistor circuits. Int. J. Circuit Theory Appl. Maria J. Avedillo, Juan Núñez
2018	—	`conf`	Inverting Versus Non-Inverting Dynamic Logic for Two-Phase Latch-free Nanopipelines. SMACD Hector J. Quintero, Manuel Jiménez Través, Maria J. Avedillo, Juan Núñez
2017	C	`conf`	Exploring logic architectures suitable for TFETs devices. ISCAS Juan Núñez, Maria J. Avedillo
2016	—	`conf`	Impact of pipeline in the power performance of tunnel transistor circuits. PATMOS Maria J. Avedillo, Juan Núñez
2016	—	`conf`	Secure cryptographic hardware implementation issues for high-performance applications. PATMOS Erica Tena-Sánchez, Antonio J. Acosta, Juan Núñez
2015	—	`conf`	An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs. LASCAS Juan Núñez, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
2014	—	`conf`	DOE based high-performance gate-level pipelines. PATMOS Juan Núñez, Maria J. Avedillo, Hector J. Quintero
2014	J	`jnl`	Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements. IEEE Trans. Very Large Scale Integr. Syst. Juan Núñez, Maria J. Avedillo, José M. Quintana
2013	C	`conf`	Novel Dynamic Gate Topology for Superpipelines in DSM Technologies. DSD Juan Núñez, Maria J. Avedillo, José M. Quintana
2013	J	`jnl`	Novel pipeline architectures based on Negative Differential Resistance devices. Microelectron. J. Juan Núñez, Maria J. Avedillo, José M. Quintana
2012	—	`conf`	Bifurcation diagrams in MOS-NDR frequency divider circuits. ICECS Juan Núñez, Maria J. Avedillo, José M. Quintana
2012	—	`conf`	Compact and Power Efficient MOS-NDR Muller C-Elements. DoCEIS Juan Núñez, Maria J. Avedillo, José M. Quintana
2012	—	`conf`	Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications. PATMOS Juan Núñez, Maria J. Avedillo, José M. Quintana
2011	—	`conf`	Efficient realization of RTD-CMOS logic gates. ACM Great Lakes Symposium on VLSI Juan Núñez, Maria J. Avedillo, José M. Quintana
2010	C	`conf`	Evaluation of RTD-CMOS Logic Gates. DSD Juan Núñez, Maria J. Avedillo, José M. Quintana
2010	C	`conf`	Single phase MOS-NDR mobile networks. ISCAS Juan Núñez, Maria J. Avedillo, José M. Quintana
2009	C	`conf`	Fast and Area Efficient Multi-input Muller C-Element based on MOS-NDR. ISCAS Juan Núñez, José M. Quintana, Maria J. Avedillo
2009	J	`jnl`	Operation Limits for RTD-Based MOBILE Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. José M. Quintana, Maria J. Avedillo, Juan Núñez, Héctor Pettenghi
2008	C	`conf`	Limits to a correct operation in RTD-based ternary inverters. ISCAS Juan Núñez, José M. Quintana, Maria J. Avedillo
2007	—	`conf`	A quasi-differential quantizer based on SMOBILE. SBCCI Juan Núñez, José M. Quintana, Maria J. Avedillo
2007	—	`conf`	Correct operation in SMOBILE-based quasi-differential quantizers. ECCTD Juan Núñez, José M. Quintana, Maria J. Avedillo
2007	—	`conf`	Limits to a Correct Evaluation in RTD-Based Quaternary Inverters. ISMVL Juan Núñez, José M. Quintana, Maria J. Avedillo
2007	—	`conf`	Operation limits in RTD-based ternary quantizers. ACM Great Lakes Symposium on VLSI Juan Núñez, José M. Quintana, Maria J. Avedillo
2006	C	`conf`	Design Guides for a Correct DC Operation in RTD-based Threshold Gates. DSD José M. Quintana, Maria J. Avedillo, Juan Núñez
2006	—	`conf`	Limits to a Correct Evaluation in RTD-based Ternary Inverters. ICECS Juan Núñez, José M. Quintana, Maria José Avedillo