Juan José Raygoza-Panduro

22 papers A 1C 2Journal 10Unranked 9
YearRankTypeTitle / Venue / Authors
2025 J jnl
Cachedia: An Environment for Efficient Cache Verification With Graphic Visualization for Debugging.
IEEE Access
Francisco J. Rodriguez-Navarrete, German Alonso Pinedo Diaz, L. A. Luna-Rodriguez, Susana Ortega-Cisneros, Luis Pizano-Escalante, Juan José Raygoza-Panduro
2025 J jnl
Digital Circuit Design for the Square Root Computation by Means of Unfolding Techniques.
IEEE Embed. Syst. Lett.
Ricardo Paez Villa, Jorge Rivera, Juan José Raygoza-Panduro, Edwin C. Becerra-Alvarez, Susana Ortega-Cisneros
2025 — conf
When AI Turns Malicious: Unethical Use of LLMs for Hardware Design.
NewCAS
Emilio Isaac Baungarten-Leon, Susana Ortega-Cisneros, Emma Mascorro-Guardado, Juan Carlos Garcia Lopez, Jorge Rivera Dominguez, Juan José Raygoza-Panduro
2024 J jnl
Vector Accelerator Unit for Caravel.
IEEE Embed. Syst. Lett.
Emilio Isaac Baungarten-Leon, Susana Ortega-Cisneros, Uriel Jaramillo-Toral, Francisco J. Rodriguez-Navarrete, Luis Pizano-Escalante, Juan José Raygoza-Panduro
2022 — conf
Implementation of 8-Channel Pulse Width Modulation with AXI4-Lite Interface.
CCE
L. A. Luna-Rodriguez, Francisco J. Rodriguez-Navarrete, Susana Ortega-Cisneros, Miguel Rivera-Acosta, Jorge Rivera Dominguez, Juan José Raygoza-Panduro
2019 J jnl
Low cost DSP-based educational embedded platform for real-time simulation and fast implementation of complex systems in Simulink.
Comput. Appl. Eng. Educ.
Emmanuel Dávila Delgado, Juan José Raygoza-Panduro, Edwin C. Becerra-Alvarez, Francisco Javier Espinoza Jurado, Eric Francisco Gutiérrez Frías
2015 A conf
A Hardware Implementation of a Unit for Geometric Algebra Operations With Parallel Memory Arrays (Abstract Only).
FPGA
Gerardo Soria García, Adrian Pedroza de-la-Crúz, Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Eduardo Bayro-Corrochano
2015 — conf
An image processor for convolution and correlation of binary images implemented in FPGA.
CCE
Susana Ortega-Cisneros, Jorge Rivera Dominguez, Pablo Moreno Villalobos, Carlos Agustin Torres C., H. Hernandez-Hector, Juan José Raygoza-Panduro
2015 — conf
Design and implementation of a DC motor control using Field Programmable Analog Arrays.
CCE
Susana Ortega-Cisneros, Juan Luis del Valle-Padilla, Ivan Emmanuel Duenas Garcia, Jorge Rivera Dominguez, Juan José Raygoza-Panduro
2015 J jnl
FPGA-based startup for AC electric drives: Application to a greenhouse ventilation system.
Comput. Ind.
Jorge Rivera, Juan José Raygoza-Panduro, Susana Ortega-Cisneros, Andrés Figueroa, Ofelia Begovich
2015 J jnl
HW/SW Co-Design of a Specific Accelerator for Robotic Computer Vision.
Computación y Sistemas
Susana Ortega-Cisneros, Miguel A. Carrazco-Díaz, Adrian Pedroza de-la-Crúz, Juan José Raygoza-Panduro, Jorge Rivera Dominguez, Federico Sandoval-Ibarra
2014 — conf
Characterization technique to implement self-timed cells for VLSI design blocks.
CCE
Susana Ortega-Cisneros, Juan José Raygoza-Panduro, José Roberto Reyes Barón, Daniel Tonali Aranda Bretón, Antonio Casillas Zamora
2014 J jnl
Discrete-time modeling and control of a boost converter by means of a variational integrator and sliding modes.
J. Frankl. Inst.
Jorge Rivera, Florentino Chavira, Alexander G. Loukianov, Susana Ortega-Cisneros, Juan José Raygoza-Panduro
2014 C conf
FPGA Implementation of a NARX Network for Modeling Nonlinear Systems.
CIARP
J. A. Rentería-Cedano, L. M. Aguilar-Lobo, Susana Ortega-Cisneros, José Raúl Loo-Yau, Juan José Raygoza-Panduro
2014 C conf
Real Time Hardware Accelerator for Image Filtering.
CIARP
Susana Ortega-Cisneros, Miguel A. Carrazco-Díaz, Adrian Pedroza de-la-Crúz, Juan José Raygoza-Panduro, Federico Sandoval-Ibarra, Jorge Rivera Dominguez
2014 — conf
Space-time AER protocol receiver asynchronously controlled on FPGA.
CCE
Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Daniel Tonali Aranda Bretón, José Roberto Reyes Barón
2012 J jnl
Copper and Core Loss Minimization for Induction Motors Using High-Order Sliding-Mode Control.
IEEE Trans. Ind. Electron.
Jorge Rivera, Christian Mora-Soto, Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Alexander G. Loukianov
2012 — conf
Super-twisting sensorless control of linear induction motors.
CCE
Alexander G. Loukianov, Jorge Rivera, Alma Y. Alanis, Juan José Raygoza-Panduro
2008 J jnl
Design of a Mathematical Unit in FPGA for the Implementation of the Control of a Magnetic Levitation System.
Int. J. Reconfigurable Comput.
Juan José Raygoza-Panduro, Susana Ortega-Cisneros, Jorge Rivera, Alberto de la Mora Gálvez
2007 J jnl
Design and Implementation of the AMCC Self-Timed Microprocessor in FPGAs.
J. Univers. Comput. Sci.
Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Alberto de la Mora Gálvez
2005 — conf
FPGA implementation of a synchronous and self-timed neuroprocessor.
ReConFig
Juan José Raygoza-Panduro, Susana Ortega-Cisneros, Eduardo I. Boemo
2005 — conf
Rapid prototyping of a self-timed ALU with FPGAs.
ReConFig
Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Juan Suardíaz Muro, Eduardo I. Boemo