Juan Antonio Maestro

120 papers A* 2A 2B 1C 5Journal 103Unranked 7
YearRankTypeTitle / Venue / Authors
2025 J jnl
Protecting the CCSDS 123.0-B-2 Compression Algorithm Against Single-Event Upsets for Space Applications.
IEEE Trans. Computers
Daniel Báscones, Francisco Garcia-Herrero, Oscar Ruano, Carlos González, Daniel Mozos, Juan Antonio Maestro
2023 J jnl
Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension.
IEEE Trans. Aerosp. Electron. Syst.
Yao-Ming Kuo, Mark F. Flanagan, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro
2023 J jnl
RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography.
IEEE Trans. Computers
Yao-Ming Kuo, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro
2022 J jnl
ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs.
IEEE Trans. Circuits Syst. II Express Briefs
Luis Alberto Aranda, Oscar Ruano, Francisco Garcia-Herrero, Juan Antonio Maestro
2022 J jnl
An analysis of FPGA configuration memory SEU accumulation and a preventative scrubbing technique.
Microprocess. Microsystems
Kyle W. Gear, Alfonso Sánchez-Macián, Juan Antonio Maestro
2022 J jnl
Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors.
Comput. Electr. Eng.
Yao-Ming Kuo, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro
2022 J jnl
Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale.
IEEE Trans. Emerg. Top. Comput.
Alfonso Sánchez-Macián, Alonso Martín-Toledano, Jefferson Andres Bravo-Montes, Francisco Garcia-Herrero, Juan Antonio Maestro
2021 J jnl
Combined Symbol Error Correction and Spare Through-Silicon Vias for 3D Memories.
IEEE Trans. Emerg. Top. Comput.
Francisco Garcia-Herrero, Alfonso Sánchez-Macián, Juan Antonio Maestro
2021 J jnl
Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and Its Derived Architectures.
IEEE Trans. Circuits Syst. II Express Briefs
Francisco Garcia-Herrero, Gary McGuire, Mark F. Flanagan, Alfonso Sánchez-Macián, Juan Antonio Maestro
2021 J jnl
Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial.
Sensors
Oscar Ruano, Francisco Garcia-Herrero, Luis Alberto Aranda, Alfonso Sánchez-Macián, Laura Rodriguez, Juan Antonio Maestro
2021 J jnl
Low delay non-binary error correction codes based on Orthogonal Latin Squares.
Integr.
Francisco Garcia-Herrero, Alfonso Sánchez-Macián, Juan Antonio Maestro
2021 J jnl
Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs.
IEEE Access
Luis Alberto Aranda, Oscar Ruano, Francisco Garcia-Herrero, Juan Antonio Maestro
2020 J jnl
An Algorithmic-Based Fault Detection Technique for the 1-D Discrete Cosine Transform.
IEEE Trans. Very Large Scale Integr. Syst.
Luis Alberto Aranda, Alfonso Sánchez-Macián, Juan Antonio Maestro
2020 — conf
Analyzing the impact of the Operating System on the Reliability of a RISC-V FPGA Implementation.
ICECS
Imran Wali, Alfonso Sánchez-Macián, Alexis Ramos, Juan Antonio Maestro
2020 J jnl
Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon's Low-Complexity Chase.
IEEE Trans. Circuits Syst.
Francisco Garcia-Herrero, Alfonso Sánchez-Macián, Juan Antonio Maestro
2020 J jnl
Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications.
IEEE Access
Luis Alberto Aranda, Francisco Garcia-Herrero, Luis Esteban, Alfonso Sánchez-Macián, Juan Antonio Maestro
2020 — conf
Reduction of Parity Overhead in a Subset of Orthogonal Latin Square Codes.
DCIS
Pedro Reviriego, Shanshan Liu, Alfonso Sánchez-Macián, Liyi Xiao, Juan Antonio Maestro
2020 J jnl
Toward a Fault-Tolerant Star Tracker for Small Satellite Applications.
IEEE Trans. Aerosp. Electron. Syst.
Luis Alberto Aranda, Pedro Reviriego, Juan Antonio Maestro
2020 J jnl
Two Behavioural Error Detection Techniques for the Cascaded Integrator-Comb Interpolation Filter Implemented on FPGA.
Circuits Syst. Signal Process.
Kyle W. Gear, Alfonso Sánchez-Macián, Francisco Garcia-Herrero, Juan Antonio Maestro
2019 J jnl
ACME: A Tool to Improve Configuration Memory Fault Injection in SRAM-Based FPGAs.
IEEE Access
Luis Alberto Aranda, Alfonso Sánchez-Macián, Juan Antonio Maestro
2019 J jnl
An ALU Protection Methodology for Soft Processors on SRAM-Based FPGAs.
IEEE Trans. Computers
Alexis Ramos, Ricardo Gonzalez-Toral, Pedro Reviriego, Juan Antonio Maestro
2019 J jnl
Enhancing Instruction TLB Resilience to Soft Errors.
IEEE Trans. Computers
Alfonso Sánchez-Macián, Luis Alberto Aranda, Pedro Reviriego, Vahdaneh Kiani, Juan Antonio Maestro
2019 J jnl
Protection Scheme for Star Tracker Images.
IEEE Trans. Aerosp. Electron. Syst.
Luis Alberto Aranda, Pedro Reviriego, Ricardo Gonzalez-Toral, Juan Antonio Maestro
2018 J jnl
A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection.
IEEE Trans. Circuits Syst. II Express Briefs
Luis Alberto Aranda, Pedro Reviriego, Juan Antonio Maestro
2018 J jnl
A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs.
IEEE Trans. Computers
Ricardo Gonzalez-Toral, Pedro Reviriego, Juan Antonio Maestro, Zhen Gao
2018 J jnl
An Efficient Fault-Tolerance Design for Integer Parallel Matrix-Vector Multiplications.
IEEE Trans. Very Large Scale Integr. Syst.
Zhen Gao, Qingqing Jing, Yumeng Li, Pedro Reviriego, Juan Antonio Maestro
2018 J jnl
Efficient Fault-Tolerant Design for Parallel Matched Filters.
IEEE Trans. Circuits Syst. II Express Briefs
Zhen Gao, Ming Zhou, Pedro Reviriego, Juan Antonio Maestro
2018 J jnl
Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs.
IEEE Trans. Computers
Alexis Ramos, Anees Ullah, Pedro Reviriego, Juan Antonio Maestro
2018 J jnl
Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes.
Microelectron. Reliab.
Shanshan Liu, Pedro Reviriego, Juan Antonio Maestro, Liyi Xiao
2018 J jnl
Modular fault tolerant processor architecture on a SoC for space.
Microelectron. Reliab.
Jesús Tabero, Alberto Regadío, César Pérez, Jesús Pazos, Pedro Reviriego, Alfonso Sánchez-Macián, Juan Antonio Maestro
2018 J jnl
Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ricardo Gonzalez-Toral, Shanshan Liu, Pedro Reviriego, Juan Antonio Maestro
2018 J jnl
Seu and Sefi error detection and correction on a ddr3 memory system.
Microelectron. Reliab.
Ana Cóbreces, Alberto Regadío, Jesús Tabero, Pedro Reviriego, Alfonso Sánchez-Macián, Juan Antonio Maestro
2017 J jnl
A Scheme to Improve the Intrinsic Error Detection of the Instruction Set Architecture.
IEEE Comput. Archit. Lett.
Jorge A. Martínez, Juan Antonio Maestro, Pedro Reviriego
2017 J jnl
A Scheme to Reduce the Number of Parity Check Bits in Orthogonal Latin Square Codes.
IEEE Trans. Reliab.
Pedro Reviriego, Shanshan Liu, Alfonso Sánchez-Macián, Liyi Xiao, Juan Antonio Maestro
2017 J jnl
A method to protect Cuckoo filters from soft errors.
Microelectron. Reliab.
Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro
2017 J jnl
A method to recover critical bits under a double error in SEC-DED protected memories.
Microelectron. Reliab.
Shanshan Liu, Pedro Reviriego, Liyi Xiao, Juan Antonio Maestro
2017 J jnl
Characterizing a RISC-V SRAM-based FPGA implementation against Single Event Upsets using fault injection.
Microelectron. Reliab.
Alexis Ramos, Juan Antonio Maestro, Pedro Reviriego
2017 J jnl
Combined Modular Key and Data Error Protection for Content-Addressable Memories.
IEEE Trans. Computers
Alfonso Sánchez-Macián, Pedro Reviriego, Juan Antonio Maestro
2017 J jnl
Comments on "Extend orthogonal Latin square codes for 32-bit data protection in memory applications" Microelectron. Reliab. 63 278-283 (2016).
Microelectron. Reliab.
Shanshan Liu, Pedro Reviriego, Alfonso Sánchez-Macián, Juan Antonio Maestro, Liyi Xiao
2017 J jnl
Single Event Transient Tolerant Bloom Filter Implementations.
IEEE Trans. Computers
Alfonso Sánchez-Macián, Pedro Reviriego, Juan Antonio Maestro, Shanshan Liu
2016 J jnl
A Comment on "Fast Bloom Filters and Their Generalization".
IEEE Trans. Parallel Distributed Syst.
Pedro Reviriego, Kenneth J. Christensen, Juan Antonio Maestro
2016 J jnl
A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits.
IEEE Trans. Circuits Syst. II Express Briefs
Pedro Reviriego, Mustafa Demirci, Adrian Evans, Juan Antonio Maestro
2016 J jnl
An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24, 12) Extended Golay Code.
IEEE Trans. Very Large Scale Integr. Syst.
Pedro Reviriego, Shanshan Liu, Liyi Xiao, Juan Antonio Maestro
2016 J jnl
Combined SEU and SEFI Protection for Memories Using Orthogonal Latin Square Codes.
IEEE Trans. Circuits Syst. I Regul. Pap.
Alfonso Sánchez-Macián, Pedro Reviriego, Juan Antonio Maestro
2016 J jnl
DMR +: An efficient alternative to TMR to protect registers in Xilinx FPGAs.
Microelectron. Reliab.
Pedro Reviriego, Mustafa Demirci, Jesús Tabero, Alberto Regadío, Juan Antonio Maestro
2016 C conf
Efficient fault tolerant parallel matrix-vector multiplications.
IOLTS
Zhen Gao, Pedro Reviriego, Juan Antonio Maestro
2016 J jnl
Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks.
IEEE Trans. Very Large Scale Integr. Syst.
Zhen Gao, Pedro Reviriego, Zhan Xu, Xin Su, Ming Zhao, Jing Wang, Juan Antonio Maestro
2016 J jnl
Implementing Double Error Correction Orthogonal Latin Squares Codes in SRAM-based FPGAs.
Microelectron. Reliab.
Mustafa Demirci, Pedro Reviriego, Juan Antonio Maestro
2016 J jnl
Improving counting Bloom filter performance with fingerprints.
Inf. Process. Lett.
Salvatore Pontarelli, Pedro Reviriego, Juan Antonio Maestro
2016 J jnl
Optimizing the Implementation of SEC-DAEC Codes in FPGAs.
IEEE Trans. Very Large Scale Integr. Syst.
Alfonso Sánchez-Macián, Pedro Reviriego, Juan Antonio Maestro
2016 J jnl
Parallel d-Pipeline: A Cuckoo Hashing Implementation for Increased Throughput.
IEEE Trans. Computers
Salvatore Pontarelli, Pedro Reviriego, Juan Antonio Maestro
2016 J jnl
Unequal Error Protection Codes Derived from Double Error Correction Orthogonal Latin Square Codes.
IEEE Trans. Computers
Mustafa Demirci, Pedro Reviriego, Juan Antonio Maestro
2015 J jnl
A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes.
IEEE Trans. Very Large Scale Integr. Syst.
Pedro Reviriego, Salvatore Pontarelli, Adrian Evans, Juan Antonio Maestro
2015 J jnl
A Synergetic Use of Bloom Filters for Error Detection and Correction.
IEEE Trans. Very Large Scale Integr. Syst.
Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, Marco Ottavi
2015 — conf
A method to protect Bloom filters from soft errors.
DFTS
Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, Marco Ottavi
2015 J jnl
Efficient Coding Schemes for Fault-Tolerant Parallel Filters.
IEEE Trans. Circuits Syst. II Express Briefs
Zhen Gao, Pedro Reviriego, Zhan Xu, Xin Su, Jing Wang, Juan Antonio Maestro
2015 J jnl
Fault Tolerant Parallel Filters Based on Error Correction Codes.
IEEE Trans. Very Large Scale Integr. Syst.
Zhen Gao, Pedro Reviriego, Wen Pan, Zhan Xu, Ming Zhao, Jing Wang, Juan Antonio Maestro
2015 J jnl
Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes.
IEEE Trans. Computers
Salvatore Pontarelli, Pedro Reviriego, Marco Ottavi, Juan Antonio Maestro
2015 J jnl
MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error Correction.
IEEE Trans. Very Large Scale Integr. Syst.
Luis J. Saiz-Adalid, Pedro Reviriego, Pedro J. Gil, Salvatore Pontarelli, Juan Antonio Maestro
2014 J jnl
A Method to Extend Orthogonal Latin Square Codes.
IEEE Trans. Very Large Scale Integr. Syst.
Pedro Reviriego, Salvatore Pontarelli, Alfonso Sánchez-Macián, Juan Antonio Maestro
2014 J jnl
A fault tolerant implementation of the Goertzel algorithm.
Microelectron. Reliab.
Zhen Gao, Pedro Reviriego, X. Li, Juan Antonio Maestro, Ming Zhao, J. Wang
2014 J jnl
An experimental power profile of Energy Efficient Ethernet switches.
Comput. Commun.
Vijay Sivaraman, Pedro Reviriego, Zhi Zhao, Alfonso Sánchez-Macián, Arun Vishwanath, Juan Antonio Maestro, Craig Russell
2014 J jnl
Efficient Flow Sampling With Back-Annotated Cuckoo Hashing.
IEEE Commun. Lett.
Salvatore Pontarelli, Pedro Reviriego, Juan Antonio Maestro
2014 J jnl
Efficient implementation of error correction codes in hash tables.
Microelectron. Reliab.
Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, Marco Ottavi
2014 J jnl
Energy Efficient Exact Matching for Flow Identification with Cuckoo Affinity Hashing.
IEEE Commun. Lett.
Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro
2014 J jnl
Exploiting processor features to implement error detection in reduced precision matrix multiplications.
Microprocess. Microsystems
Pedro Reviriego, Serdar Zafer Can, Çagri Eryilmaz, Juan Antonio Maestro, Oguz Ergin
2014 J jnl
Optimized parallel decoding of difference set codes for high speed memories.
Microelectron. Reliab.
Mustafa Demirci, Pedro Reviriego, Juan Antonio Maestro
2013 J jnl
A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, Marco Ottavi
2013 J jnl
An Efficient Technique to Protect Serial Shift Registers Against Soft Errors.
IEEE Trans. Circuits Syst. II Express Briefs
Pedro Reviriego, Oscar Ruano, Mark F. Flanagan, Salvatore Pontarelli, Juan Antonio Maestro
2013 J jnl
Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation.
IEEE Trans. Very Large Scale Integr. Syst.
Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro
2013 J jnl
Diverse Double Modular Redundancy: A New Direction for Soft-Error Detection and Correction.
IEEE Des. Test
Pedro Reviriego, Chris J. Bleakley, Juan Antonio Maestro
2013 J jnl
Efficient Arithmetic-Residue-Based SEU-Tolerant FIR Filter Design.
IEEE Trans. Circuits Syst. II Express Briefs
Zhen Gao, Pedro Reviriego, Wen Pan, Zhan Xu, Ming Zhao, Jing Wang, Juan Antonio Maestro
2013 J jnl
Enhanced Duplication: a Technique to Correct Soft Errors in Narrow Values.
IEEE Comput. Archit. Lett.
Burak Karsli, Pedro Reviriego, M. Fatih Balli, Oguz Ergin, Juan Antonio Maestro
2013 J jnl
Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes.
IEEE Trans. Very Large Scale Integr. Syst.
Pedro Reviriego, Juan Antonio Maestro, Mark F. Flanagan
2013 — conf
Implementing triple adjacent Error Correction in double error correction Orthogonal Latin Squares Codes.
DFTS
Pedro Reviriego, Shih-Fu Liu, Juan Antonio Maestro, S. Lee, Nur A. Touba, Rudrajit Datta
2013 J jnl
Low Complexity Concurrent Error Detection for Complex Multiplication.
IEEE Trans. Computers
Salvatore Pontarelli, Pedro Reviriego, Chris J. Bleakley, Juan Antonio Maestro
2013 J jnl
Reducing the Cost of Implementing Error Correction Codes in Content Addressable Memories.
IEEE Trans. Circuits Syst. II Express Briefs
Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, Marco Ottavi
2013 J jnl
Soft error tolerant Content Addressable Memories (CAMs) using error detection codes and duplication.
Microprocess. Microsystems
Juan Antonio Maestro, Pedro Reviriego, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong
2013 J jnl
Using Single Error Correction Codes to Protect Against Isolated Defects and Soft Errors.
IEEE Trans. Reliab.
Costas Argyrides, Pedro Reviriego, Juan Antonio Maestro
2012 — conf
An energy consumption model for Energy Efficient Ethernet switches.
HPCS
Pedro Reviriego, Vijay Sivaraman, Zhi Zhao, Juan Antonio Maestro, Arun Vishwanath, Alfonso Sánchez-Macián, Craig Russell
2012 J jnl
Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Shih-Fu Liu, Pedro Reviriego, Juan Antonio Maestro
2012 J jnl
Efficient error detection in Double Error Correction BCH codes for memory applications.
Microelectron. Reliab.
Pedro Reviriego, Costas Argyrides, Juan Antonio Maestro
2012 J jnl
Implementing Concurrent Error Detection in Infinite-Impulse-Response Filters.
IEEE Trans. Circuits Syst. II Express Briefs
Pedro Reviriego, Oscar Ruano, Juan Antonio Maestro
2012 C conf
Low Power embedded DRAM caches using BCH code partitioning.
IOLTS
Pedro Reviriego, Alfonso Sánchez-Macián, Juan Antonio Maestro
2012 J jnl
Multiple Cell Upset Correction in Memories Using Difference Set Codes.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pedro Reviriego, Mark F. Flanagan, Shih-Fu Liu, Juan Antonio Maestro
2012 J jnl
Network monitoring for energy efficiency in large-scale networks: the case of the Spanish Academic Network.
J. Supercomput.
José Luis García-Dorado, Eduardo Magaña, Pedro Reviriego, Mikel Izal, Daniel Morató, Juan Antonio Maestro, Javier Aracil, Jorge E. López de Vergara
2012 J jnl
Study of the potential energy savings in Ethernet by combining Energy Efficient Ethernet and Adaptive Link Rate.
Trans. Emerg. Telecommun. Technol.
Pedro Reviriego, Juan Antonio Maestro, José Alberto Hernández, David Larrabeiti
2011 J jnl
A fast and efficient technique to apply Selective TMR through optimization.
Microelectron. Reliab.
Oscar Ruano, Juan Antonio Maestro, Pedro Reviriego
2011 J jnl
An Initial Evaluation of Energy Efficient Ethernet.
IEEE Commun. Lett.
Pedro Reviriego, Ken Christensen, Juan Rabanillo, Juan Antonio Maestro
2011 A* conf
Designing ad-hoc scrubbing sequences to improve memory reliability against soft errors.
DAC
Pedro Reviriego, Juan Antonio Maestro, Sanghyeon Baeg
2011 J jnl
Fault Tolerant Single Error Correction Encoders.
J. Electron. Test.
Juan Antonio Maestro, Pedro Reviriego, Costas Argyrides, Dhiraj K. Pradhan
2011 J jnl
Implications of energy efficient Ethernet for hubs and switches.
Int. J. Commun. Networks Distributed Syst.
Pedro Reviriego, Juan Antonio Maestro, Chris J. Bleakley
2011 J jnl
Low-complexity Concurrent Error Detection for convolution with Fast Fourier Transforms.
Microelectron. Reliab.
Chris J. Bleakley, Pedro Reviriego, Juan Antonio Maestro
2011 J jnl
Mitigating the effects of large multiple cell upsets (MCUs) in memories.
ACM Trans. Design Autom. Electr. Syst.
Juan Antonio Maestro, Pedro Reviriego, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong
2011 J jnl
Mitigation of permanent faults in adaptive equalizers.
Microelectron. Reliab.
Pedro Reviriego, Shanshan Liu, Juan Antonio Maestro
2011 J jnl
Offset DMR: A Low Overhead Soft Error Detection and Correction Technique for Transform-Based Convolution.
IEEE Trans. Computers
Pedro Reviriego, Chris J. Bleakley, Juan Antonio Maestro, Anne O'Donnell
2011 — conf
On the Impact of the TCP Acknowledgement Frequency on Energy Efficient Ethernet Performance.
Networking Workshops
Pedro Reviriego, Alfonso Sánchez-Macián, Juan Antonio Maestro
2011 J jnl
On the expected longest length probe sequence for hashing with separate chaining.
J. Discrete Algorithms
Pedro Reviriego, Lars Holst, Juan Antonio Maestro
2011 J jnl
Structural DMR: A Technique for Implementation of Soft-Error-Tolerant FIR Filters.
IEEE Trans. Circuits Syst. II Express Briefs
Pedro Reviriego, Chris J. Bleakley, Juan Antonio Maestro
2011 J jnl
Towards an energy efficient 10 Gb/s optical ethernet: Performance analysis and viability.
Opt. Switch. Netw.
David Larrabeiti, Pedro Reviriego, José Alberto Hernández, Juan Antonio Maestro, Manuel Urueña
2011 B conf
Using Coordinated Transmission with Energy Efficient Ethernet.
Networking (1)
Pedro Reviriego, Ken Christensen, Alfonso Sánchez-Macián, Juan Antonio Maestro
2011 C conf
Validation and optimization of TMR protections for circuits in radiation environments.
DDECS
Oscar Ruano, Juan Antonio Maestro, Pedro Reviriego
2010 J jnl
Burst Transmission for Energy-Efficient Ethernet.
IEEE Internet Comput.
Pedro Reviriego, José Alberto Hernández, David Larrabeiti, Juan Antonio Maestro
2010 J jnl
Efficient Soft Error-Tolerant Adaptive Equalizers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pedro Reviriego, Juan Antonio Maestro, Shih-Fu Liu
2010 J jnl
Energy Efficiency in Industrial Ethernet: The Case of Powerlink.
IEEE Trans. Ind. Electron.
Juan Antonio Maestro, Pedro Reviriego
2010 J jnl
IEEE 802.3az: the road to energy efficient ethernet.
IEEE Commun. Mag.
Ken Christensen, Pedro Reviriego, Bruce Nordman, Michael Bennett, Mehrgan Mostowfi, Juan Antonio Maestro
2010 J jnl
Reliability analysis of memories protected with BICS and a per-word parity bit.
ACM Trans. Design Autom. Electr. Syst.
Pedro Reviriego, Juan Antonio Maestro, Chris J. Bleakley
2009 J jnl
A method to eliminate the event accumulation problem from a memory affected by multiple bit upsets.
Microelectron. Reliab.
Juan Antonio Maestro, Pedro Reviriego
2009 J jnl
Efficient error detection codes for multiple-bit upset correction in SRAMs with BICS.
ACM Trans. Design Autom. Electr. Syst.
Pedro Reviriego, Juan Antonio Maestro
2009 J jnl
Performance evaluation of energy efficient ethernet.
IEEE Commun. Lett.
Pedro Reviriego, José Alberto Hernández, David Larrabeiti, Juan Antonio Maestro
2009 J jnl
Protection against soft errors in the space environment: A finite impulse response (FIR) filter case study.
Integr.
Juan Antonio Maestro, Pedro Reviriego, Pilar Reyes, Oscar Ruano
2009 J jnl
Reliability of Single-Error Correction Protected Memories.
IEEE Trans. Reliab.
Juan Antonio Maestro, Pedro Reviriego
2009 C conf
Soft error detection and correction for FFT based convolution using different block lengths.
IOLTS
Pedro Reviriego, Juan Antonio Maestro, Anne O'Donnell, Chris J. Bleakley
2008 J jnl
Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study.
J. Signal Process. Syst.
Pilar Reyes, Pedro Reviriego, Juan Antonio Maestro, Oscar Ruano
2008 A* conf
Study of the effects of MBUs on the reliability of a 150 nm SRAM device.
DAC
Juan Antonio Maestro, Pedro Reviriego
2007 C conf
An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques.
DDECS
Oscar Ruano, Pilar Reyes, Juan Antonio Maestro, Luca Sterpone, Pedro Reviriego
2004 J jnl
New Alternatives to the Estimation Problem in Hardware-Software Codesign of Complex Embedded Systems: The H.261 Video Co-dec Case Study.
Des. Autom. Embed. Syst.
Juan Antonio Maestro, Daniel Mozos, Raquel Dormido, Pedro Reviriego
1999 A conf
The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach.
DATE
Juan Antonio Maestro, Daniel Mozos, Román Hermida
1998 — conf
A Grouping Partitioning Technique with Automatic Criterion Selection for the Codesign Proces.
EUROMICRO
Juan Antonio Maestro, Daniel Mozos, Julio Septién
1998 A conf
A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process.
DATE
Juan Antonio Maestro, Daniel Mozos, Hortensia Mecha