Juan A. López

18 papers A 1B 1C 1Journal 6Unranked 9
YearRankTypeTitle / Venue / Authors
2023 — conf
Any-Radix Efficient Fully-Parallel Implementation of the Fast Fourier Transform on FPGAs.
DCIS
Ignacio Amat Hernández, Juan A. López
2014 — conf
Automated Data Flow Graph Partitioning for a Hierarchical Approach to Wordlength Optimization.
ARC
Enrique Sedano, Daniel Ménard, Juan A. López
2014 J jnl
Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes.
J. Syst. Archit.
Pablo Barrio, Carlos Carreras, Juan A. López, Óscar Robles, Ruzica Jevtic, Roberto Sierra
2012 J jnl
Quantization of VLSI digital signal processing systems.
EURASIP J. Adv. Signal Process.
Gabriel Caffarena, Olivier Sentieys, Daniel Ménard, Juan A. López, David Novo
2010 — conf
Fast Fixed-Point Optimization of DSP Algorithms.
VLSI-SoC (Selected Papers)
Gabriel Caffarena, Angel Fernandez Herrero, Juan A. López, Carlos Carreras
2010 C conf
Fast fixed-point optimization of DSP algorithms.
VLSI-SoC
Gabriel Caffarena, Carlos Carreras, Juan A. López, Angel Fernandez Herrero
2010 J jnl
SQNR Estimation of Fixed-Point DSP Algorithms.
EURASIP J. Adv. Signal Process.
Gabriel Caffarena, Carlos Carreras, Juan A. López, Angel Fernandez Herrero
2010 — conf
SQNR estimation of non-linear fixed-point algorithms.
EUSIPCO
Gabriel Caffarena, Juan A. López, Angel Fernandez Herrero, Carlos Carreras
2009 J jnl
Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs.
Int. J. Reconfigurable Comput.
Gabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, Octavio Nieto-Taladriz
2008 J jnl
Fast and accurate computation of the roundoff noise of linear time-invariant systems.
IET Circuits Devices Syst.
Juan A. López, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz
2008 — conf
Optimized Architectural Synthesis of Fixed-Point Datapaths.
ReConFig
Gabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, Octavio Nieto-Taladriz
2007 J jnl
Improved Interval-Based Characterization of Fixed-Point LTI Systems With Feedback Loops.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz
2006 B conf
High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs.
FPL
Gabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz
2006 — conf
Optimized Synthesis of DSP Cores Combining Logic-based and Embedded FPGA Resources.
SoC
Gabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz
2004 — conf
Analysis of limit cycles by means of affine arithmetic computer-aided tests.
EUSIPCO
Juan A. López, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz
2004 A conf
High-speed systolic array for gene matching.
FPGA
Gabriel Caffarena, Slobodan Bojanic, Juan A. López, Carlos E. Pedreira, Octavio Nieto-Taladriz
2003 — conf
Fast characterization of the noise bounds derived from coefficient and signal quantization.
ISCAS (4)
Juan A. López, Carlos Carreras, Gabriel Caffarena, Octavio Nieto-Taladriz
1999 — conf
Bit-Width Selection for Data-Path Implementations.
ISSS
Carlos Carreras, Juan A. López, Octavio Nieto-Taladriz