Ju-Yueh Lee

12 papers A 4B 1C 1Journal 2Unranked 4
YearRankTypeTitle / Venue / Authors
2016 — conf
In-place LUT polarity inVersion to mitigate soft errors for FPGAs.
DFT
Juexiao Su, Ju-Yueh Lee, Chang Wu, Lei He
2012 — conf
Heterogeneous configuration memory scrubbing for soft error mitigation in FPGAs.
FPT
Ju-Yueh Lee, Cheng-Ru Chang, Naifeng Jing, Juexiao Su, Shi-Jie Wen, Rick Wong, Lei He
2012 J jnl
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms.
ACM Trans. Design Autom. Electr. Syst.
Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Lei He
2011 A conf
Fault modeling and characteristics of SRAM-based FPGAs (abstract only).
FPGA
Naifeng Jing, Ju-Yueh Lee, Chun Zhang, Jiarong Tong, Zhigang Mao, Lei He
2011 J jnl
In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wenyao Xu, Jia Wang, Yu Hu, Ju-Yueh Lee, Fang Gong, Lei He, Majid Sarrafzadeh
2011 A conf
Mitigating FPGA interconnect soft errors by in-place LUT inversion.
ICCAD
Naifeng Jing, Ju-Yueh Lee, Weifeng He, Zhigang Mao, Lei He
2011 B conf
Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms.
FPL
Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Shi-Jie Wen, Rick Wong, Lei He
2010 — conf
Fault-tolerant resynthesis with dual-output LUTs.
ASP-DAC
Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, Minming Li
2010 A conf
In-place decomposition for robustness in FPGA.
ICCAD
Ju-Yueh Lee, Zhe Feng, Lei He
2010 A conf
RALF: Reliability Analysis for Logic Faults - An exact algorithm and its applications.
DATE
Samuel B. Luckenbill, Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He
2009 — conf
Simultaneous test pattern compaction, ordering and X-filling for testing power reduction.
ISQED
Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He
2006 C conf
Low power scheduling method using multiple supply voltages.
ISCAS
Kun-Lin Tsai, Ju-Yueh Lee, Shanq-Jang Ruan, Feipei Lai