Jri Lee - RankMe

45 papers Journal 22Unranked 23

Year	Rank	Type	Title / Venue / Authors
2017	—	`conf`	6.1 A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS. ISSCC Pen-Jui Peng, Jeng-Feng Li, Li-Yang Chen, Jri Lee
2015	J	`jnl`	4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology. IEEE J. Solid State Circuits Ping-Chuan Chiang, Jhih-Yu Jiang, Hao-Wei Hung, Chin-Yang Wu, Gaun-Sing Chen, Jri Lee
2015	—	`conf`	56Gb/s PAM4 and NRZ SerDes transceivers in 40nm CMOS. VLSIC Jri Lee, Ping-Chuan Chiang, Chih-Chi Weng
2015	J	`jnl`	A 94 GHz 3D Image Radar Engine With 4TX/4RX Beamforming Scan Technique in 65 nm CMOS Technology. IEEE J. Solid State Circuits Pen-Jui Peng, Pang-Ning Chen, Chiro Kao, Yu-Lun Chen, Jri Lee
2015	—	`conf`	CW/FMCW/pulse radar engines for 24/26GHz multi-standard applications in 65nm CMOS. A-SSCC Li-Yang Chen, Pen-Jui Peng, Chiro Kao, Yu-Lun Chen, Jri Lee
2015	J	`jnl`	Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies. IEEE J. Solid State Circuits Jri Lee, Ping-Chuan Chiang, Pen-Jui Peng, Li-Yang Chen, Chih-Chi Weng
2014	—	`conf`	2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS. ISSCC Ping-Chuan Chiang, Hao-Wei Hung, Hsiang-Yun Chu, Guan-Sing Chen, Jri Lee
2014	—	`conf`	A 94GHz duobinary keying wireless transceiver in 65nm CMOS. VLSIC Yu-Lun Chen, Chiro Kao, Pen-Jui Peng, Jri Lee
2014	—	`conf`	Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology. A-SSCC Guan-Sing Chen, Chin-Yang Wu, Chen-Lun Lin, Hao-Wei Hung, Jri Lee
2013	—	`conf`	100Gb/s ethernet chipsets in 65nm CMOS technology. ISSCC Jhih-Yu Jiang, Ping-Chuan Chiang, Hao-Wei Hung, Chen-Lun Lin, Ty Yoon, Jri Lee
2013	—	`conf`	A 94GHz 3D-image radar engine with 4TX/4RX beamforming scan technique in 65nm CMOS. ISSCC Pang-Ning Chen, Pen-Jui Peng, Chiro Kao, Yu-Lun Chen, Jri Lee
2012	J	`jnl`	A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology. IEEE J. Solid State Circuits Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee
2011	—	`conf`	A 40Gb/s TX and RX chip set in 65nm CMOS. ISSCC Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee
2011	—	`conf`	An 87GHz QPSK transceiver with costas-loop carrier recovery in 65nm CMOS. ISSCC Shih-Jou Huang, Yu-Ching Yeh, Huaide Wang, Pang-Ning Chen, Jri Lee
2011	—	`conf`	Tutorial: "Design of high-speed wireline transceivers". SoCC Jri Lee
2011	J	`jnl`	W-Band BPSK and QPSK Transceivers With Costas-Loop Carrier Recovery in 65-nm CMOS Technology. IEEE J. Solid State Circuits Shih-Jou Huang, Yu-Ching Yeh, Huaide Wang, Pang-Ning Chen, Jri Lee
2010	J	`jnl`	A 2 , ˟, 25-Gb/s Receiver With 2: 5 DMUX for 100-Gb/s Ethernet. IEEE J. Solid State Circuits Ke-Chung Wu, Jri Lee
2010	J	`jnl`	A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology. IEEE J. Solid State Circuits Huaide Wang, Jri Lee
2010	—	`conf`	A 2×25Gb/s deserializer with 2∶5 DMUX for 100Gb/s ethernet applications. ISSCC Ke-Chung Wu, Jri Lee
2010	J	`jnl`	A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology. IEEE J. Solid State Circuits Jri Lee, Yi-An Li, Meng-Hsiung Hung, Shih-Jou Huang
2010	J	`jnl`	A Low-Power Low-Cost Fully-Integrated 60-GHz Transceiver System With OOK Modulation and On-Board Antenna Assembly. IEEE J. Solid State Circuits Jri Lee, Yentso Chen, Yenlin Huang
2010	—	`conf`	A fully integrated 77GHz FMCW radar system in 65nm CMOS. ISSCC Yi-An Li, Meng-Hsiung Hung, Shih-Jou Huang, Jri Lee
2009	J	`jnl`	A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition. IEEE J. Solid State Circuits Jri Lee, Ke-Chung Wu
2009	—	`conf`	A 20Gb/s full-rate linear CDR circuit with automatic frequency acquisition. ISSCC Jri Lee, Ke-Chung Wu
2009	—	`conf`	A low-power fully integrated 60GHz transceiver system with OOK modulation and on-board antenna assembly. ISSCC Jri Lee, Yenlin Huang, Yentso Chen, Hsinchia Lu, Chiajung Chang
2009	J	`jnl`	Study of Subharmonically Injection-Locked PLLs. IEEE J. Solid State Circuits Jri Lee, Huaide Wang
2009	—	`conf`	Subharmonically injection-locked PLLs for ultra-low-noise clock generation. ISSCC Jri Lee, Huaide Wang, Wen-Tsao Chen, Yung-Pin Lee
2008	J	`jnl`	A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique. IEEE J. Solid State Circuits Jri Lee, Mingchung Liu
2008	—	`conf`	A 20Gb/s Duobinary Transceiver in 90nm CMOS. ISSCC Jri Lee, Ming-Shuan Chen, Huaide Wang
2008	J	`jnl`	A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology. IEEE J. Solid State Circuits Jri Lee, Mingchung Liu, Huaide Wang
2008	J	`jnl`	Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data. IEEE J. Solid State Circuits Jri Lee, Ming-Shuan Chen, Huaide Wang
2008	J	`jnl`	Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits Sanroku Tsukamoto, Shen-Iuan Liu, Stefan Heinen, Roland Thewes, Jri Lee
2007	—	`conf`	A 20Gb/s Broadband Transmitter with Auto-Configuration Technique. ISSCC Jri Lee, Huaide Wang
2007	—	`conf`	A 20Gb/s Burst-Mode CDR Circuit Using Injection-Locking Technique. ISSCC Jri Lee, Mingchung Liu
2007	—	`conf`	A 75-GHz PLL in 90-nm CMOS Technology. ISSCC Jri Lee
2007	—	`conf`	Gigabit CDRs Equalizers. ISSCC John T. Stonick, Jri Lee
2006	J	`jnl`	A 20-Gb/s Adaptive Equalizer in 0.13-$muhbox m$CMOS Technology. IEEE J. Solid State Circuits Jri Lee
2006	—	`conf`	A 20Gb/s Adaptive Equalizer in 0.13µm CMOS Technology. ISSCC Jri Lee
2006	J	`jnl`	A 3-to-8-GHz fast-hopping frequency synthesizer in 0.18-μm CMOS technology. IEEE J. Solid State Circuits Jri Lee
2006	J	`jnl`	High-speed circuit designs for transmitters in broadband data links. IEEE J. Solid State Circuits Jri Lee
2005	J	`jnl`	Correction to "A 40-Gb/s Clock and Data Recovery Circuit in 0.18μm CMOS Technology". IEEE J. Solid State Circuits Jri Lee, Behzad Razavi
2004	J	`jnl`	A 40-GHz frequency divider in 0.18-μm CMOS technology. IEEE J. Solid State Circuits Jri Lee, Behzad Razavi
2004	J	`jnl`	Analysis and modeling of bang-bang clock and data recovery circuits. IEEE J. Solid State Circuits Jri Lee, Kenneth S. Kundert, Behzad Razavi
2003	J	`jnl`	A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology. IEEE J. Solid State Circuits Jri Lee, Behzad Razavi
2003	—	`conf`	Modeling of jitter in bang-bang clock and data recovery circuits. CICC Jri Lee, Kenneth S. Kundert, Behzad Razavi