João Paulo Teixeira

107 papers A 12B 5C 20Misc 5Journal 25Unranked 39

Year	Rank	Type	Title / Venue / Authors
2020	—	`ch.`	Internet of Things and Artificial Intelligence - A Wining Partnership? Convergence of Artificial Intelligence and the Internet of Things Jorge Semião, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2018	—	`conf`	Performance Sensor for Reliable Operation. HCI (8) Jorge Semião, Ruben Cabral, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2015	J	`jnl`	Fault-Tolerance in Field Programmable Gate Array with Dynamic Voltage and Frequency Scaling. J. Low Power Electron. Carlos Leong, Jorge Semião, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2015	—	`conf`	Fault-tolerance in FPGA focusing power reduction or performance enhancement. LATS Carlos Leong, Jorge Semião, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2014	—	`conf`	Performance sensor for tolerance and predictive detection of delay-faults. DFT Jorge Semião, David Saraiva, Carlos Leong, André Romão, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2013	B	`conf`	Aging monitoring with local sensors in FPGA-based designs. FPL Carlos Leong, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira, María Dolores Valdés, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas
2013	J	`jnl`	Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion. J. Electron. Test. Julio César Vázquez, Víctor H. Champac, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira
2012	J	`jnl`	Aging-Aware Power or Frequency Tuning With Predictive Fault Detection. IEEE Des. Test Comput. Jackson Pachito, Celestino V. Martins, Bruno Jacinto, Jorge Semião, Julio César Vázquez, Víctor H. Champac, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2012	J	`jnl`	Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits. J. Electron. Test. Judit Freijedo, Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira
2012	C	`conf`	The influence of clock-gating on NBTI-induced delay degradation. IOLTS Jackson Pachito, Celestino V. Martins, Jorge Semião, Marcelino Bicho Dos Santos, Isabel C. Teixeira, João Paulo Teixeira
2011	Misc	`conf`	Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors. VTS Celestino V. Martins, Jorge Semião, Julio César Vázquez, Víctor H. Champac, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2011	J	`jnl`	Lower J. Low Power Electron. Judit Freijedo, María Dolores Valdés, Lucía Costas, María José Moure, Juan J. Rodríguez-Andina, Jorge Semião, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira
2011	—	`conf`	Modeling the effect of process variations on the timing response of nanometer digital circuits. LATW Judit Freijedo, Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira
2011	J	`jnl`	On-Line BIST for Performance Failure Prediction Under NBTI-Induced Aging in Safety-Critical Applications. J. Low Power Electron. R. S. Oliveira, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira
2011	—	`conf`	On-line BIST for performance failure prediction under aging effects in automotive safety-critical applications. LATW R. S. Oliveira, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira
2011	B	`conf`	Performance Failure Prediction Using Built-In Delay Sensors in FPGAs. FPL Vasco Bexiga, Carlos Leong, Jorge Semião, Isabel C. Teixeira, João Paulo Teixeira, María Dolores Valdés, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas
2011	—	`conf`	Programmable sensor for on-line checking of signal integrity in FPGA-based systems subject to aging effects. LATW María Dolores Valdés, Judit Freijedo, María José Moure, Juan J. Rodríguez-Andina, Jorge Semião, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira
2010	C	`conf`	Automatic Configuration of a Medical Imaging System to Unknown Delays in Synchronous Input Data Channels. ISCAS Carlos Leong, João Paulo Teixeira, Isabel C. Teixeira, Ricardo Bugalho, Manuel Ferreira, Pedro Miguel Rodrigues, José C. Silva, Pedro Lousã, João Varela
2010	C	`conf`	Built-in Clock Domain Crossing (CDC) test and diagnosis in GALS systems. DDECS Carlos Leong, Pedro Machado, Vasco Bexiga, João Paulo Teixeira, Isabel C. Teixeira, José C. Silva, Pedro Lousã, João Varela
2010	J	`jnl`	Impact of Power Supply Voltage Variations on FPGA-Based Digital Systems Performance. J. Low Power Electron. Judit Freijedo, Lucía Costas, Jorge Semião, Juan J. Rodríguez-Andina, María José Moure, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira
2010	C	`conf`	Investigating the Use of BICS to detect resistive-open defects in SRAMs. IOLTS Raul Chipana, Letícia Maria Veiras Bolzani, Fabian Vargas, Jorge Semião, Juan J. Rodríguez-Andina, Isabel C. Teixeira, João Paulo Teixeira
2010	Misc	`conf`	Low-sensitivity to process variations aging sensor for automotive safety-critical applications. VTS Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Isabel Maria Cacho Teixeira, Marcelino B. Santos, João Paulo Teixeira
2010	C	`conf`	Predictive error detection by on-line aging monitoring. IOLTS Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira
2010	A	`conf`	Programmable aging sensor for automotive safety-critical applications. DATE Julio César Vázquez, Víctor H. Champac, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira
2009	C	`conf`	Built-in aging monitoring for safety-critical applications. IOLTS Julio César Vázquez, Víctor H. Champac, Adriel Ziesemer, Ricardo Reis, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira
2009	C	`conf`	Controllability and observability in mixed signal cores. IOLTS José F. da Rocha, Nuno Dias, Angelo Monteiro, Alexandre Neves, Gabriel Santos, Marcelino B. Santos, João Paulo Teixeira
2009	—	`conf`	Data Acquisition Electronics for PET Mammography Imaging. BIODEVICES Carlos Leong, Pedro Machado, Vasco Bexiga, João Paulo Teixeira, Isabel C. Teixeira, Joel Rego, Pedro Neves, Fernando Piedade, Pedro Lousã, Pedro Miguel Rodrigues, Andreia Trindade, Ricardo Bugalho, João F. Pinheiro, Manuel Ferreira, João Varela
2009	C	`conf`	Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies. IOLTS Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2009	—	`conf`	Measuring clock-signal modulation efficiency for Systems-on-Chip in electromagnetic interference environment. LATW Jorge Semião, Judit Freijedo, Marlon Moraes, M. Mallmann, Carlos Lemos Antunes, Juliano Benfica, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, Juan J. Rodríguez-Andina, João Paulo Teixeira, Daniel Lupi, Edmundo Gatti, Luis Garcia, Fernando Hernandez
2009	—	`conf`	On-Detector Electronics of the Clear PEM Scanner. BIODEVICES Edgar F. M. Albuquerque, Vasco Bexiga, Ricardo Bugalho, Bruno Carriço, Cláudia S. Ferreira, Miguel Ferreira, Joaquim Godinho, Fernando M. Gonçalves, Carlos Leong, Pedro Lousã, Pedro Machado, Rui Moura, Pedro Neves, Catarina Ortigão, Fernando Piedade, João F. Pinheiro, P. Relvas, Angelo Rivetti, Pedro Miguel Rodrigues, José C. Silva, Manuel M. Silva, Isabel C. Teixeira, João Paulo Teixeira, Andreia Trindade, João Varela
2008	J	`jnl`	Delay Modeling for Power Noise and Temperature-Aware Design and Test of Digital Systems. J. Low Power Electron. Judit Freijedo, Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira
2008	C	`conf`	Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits. IOLTS Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2008	C	`conf`	Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits. DDECS Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2008	—	`conf`	Robust solution for synchronous communication among multi clock domains. APCCAS Jorge Semião, João Varela, Judit Freijedo, Juan J. Rodríguez-Andina, Carlos Leong, João Paulo Teixeira, Isabel C. Teixeira
2008	J	`jnl`	Selected Peer-Reviewed Articles from the LPonTR 2008 Workshop. J. Low Power Electron. Alex Bystrov, João Paulo Teixeira
2008	J	`jnl`	Signal Integrity Enhancement in Digital Circuits. IEEE Des. Test Comput. Jorge Semião, Marcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Leonardo Bisch Piccoli, Fabian Vargas, Marcelino Bicho Dos Santos, Isabel Maria Cacho Teixeira, João Paulo Teixeira
2008	J	`jnl`	Time Management for Low-Power Design of Digital Systems. J. Low Power Electron. Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2007	—	`conf`	Enhancing the Tolerance to Power-Supply Instability in Digital Circuits. ISVLSI Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2007	J	`jnl`	Functional-oriented mask-based built-in self-test. IET Comput. Digit. Tech. Marcelino B. Santos, João Paulo Teixeira
2007	C	`conf`	Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits. DDECS Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2007	—	`conf`	Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations. DFT Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino Bicho Dos Santos, Isabel C. Teixeira, João Paulo Teixeira
2007	C	`conf`	On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits. IOLTS Jorge Semião, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2006	—	`conf`	BIST Architectures and Fault Emulation. LATW Abilio Parreira, Marcelino B. Santos, João Paulo Teixeira
2006	C	`conf`	Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes. IOLTS Marcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Jorge Semião, Isabel C. Teixeira, João Paulo Teixeira
2006	C	`conf`	Functional-Oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage. DDECS F. Guerreiro, Jorge Semião, A. Pierce, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2006	C	`conf`	Probabilistic Testability Analysis and DFT Methods at RTL. DDECS José M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João Paulo Teixeira
2006	—	`conf`	Using Multiple Clock Schemes and Multi-Temperature Test for Dynamic Fault Detection in Digital Systems. LATW Marcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Isabel C. Teixeira, João Paulo Teixeira
2005	B	`conf`	Design and Test Methodology for a Reconfigurable PEM Data Acquisition Electronics System. FPL Carlos Leong, P. Bento, Pedro Miguel Rodrigues, Andreia Trindade, José C. Silva, Pedro Lousã, Joel Rego, J. Nobre, João Varela, João Paulo Teixeira, Isabel C. Teixeira
2005	C	`conf`	Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test. IOLTS Marcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2005	J	`jnl`	Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip. J. Electron. Test. D. Barros Júnior, Marcial Jesús Rodríguez-Irago, Marcelino B. Santos, Isabel C. Teixeira, Fabian Vargas, João Paulo Teixeira
2004	A	`conf`	A Probabilistic Method for the Computation of Testability of RTL Constructs. DATE José M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João Paulo Teixeira
2004	J	`jnl`	Built-In Self-Test Quality Assessment Using Hardware Fault Emulation In FPGAs. Comput. Artif. Intell. Abilio Parreira, João Paulo Teixeira, Marcelino B. Santos
2004	B	`conf`	FPGAs BIST Evaluation. FPL Abilio Parreira, João Paulo Teixeira, Marcelino B. Santos
2004	C	`conf`	Modeling and Simulation of Time Domain Faults in Digital Systems. IOLTS Daniel Barros Jr., Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2004	J	`jnl`	On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level. J. Electron. Test. Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Luz Balado, Joan Figueras
2003	B	`conf`	Fault Simulation Using Partially Reconfigurable Hardware. FPL Abilio Parreira, João Paulo Teixeira, A. Pantelimon, Marcelino B. Santos, José T. de Sousa
2003	—	`conf`	Hardware/software solution for the automation and real-time control of a wine bottling production line. ETFA (1) Rui Ribeiro, Octávio Páscoa Dias, João Paulo Teixeira, Isabel C. Teixeira
2003	C	`conf`	Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems. IOLTS Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2003	A	`conf`	RTL Test Pattern Generation for High Quality Loosely Deterministic BIST. DATE Marcelino B. Santos, José M. Fernandes, Isabel C. Teixeira, João Paulo Teixeira
2002	J	`jnl`	Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System. J. Electron. Test. Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2002	—	`conf`	On High-Quality, Low Energy BIST Preparation at RT-Level. LATW Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Luz Balado, Joan Figueras
2002	J	`jnl`	RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage. J. Electron. Test. Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
2002	A	`conf`	RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. ITC Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras
2002	—	`conf`	Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling. DFT Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2001	—	`conf`	Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro. IOLTW Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2001	A	`conf`	Embedded tutorial: TRP: integrating embedded test and ATE. DATE Yervant Zorian, Paolo Prinetto, João Paulo Teixeira, Isabel C. Teixeira, Carlos Eduardo Pereira, Octávio Páscoa Dias, Jorge Semião, Peter Muhmenthaler, W. Radermacher
2001	A	`conf`	Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level. ITC Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2001	—	`conf`	RTL design validation, DFT and test pattern generation for high defects coverage. ETW Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
2001	J	`jnl`	RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems. J. Electron. Test. Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
2001	—	`conf`	Towards E-Management as Enabler for Accelerated Change. ICEIS (2) Hugo Lérias, João Luz, Pedro Moura, Ana Mendes, Isabel C. Teixeira, João Paulo Teixeira
2000	—	`conf`	Experiments on RTL ATPG and Fault Simulation for High Defect Coverage in Digital Systems-on-a-Chip. LATW Marcelino B. Santos, João Paulo Teixeira
2000	J	`jnl`	Low Power BIST by Filtering Non-Detecting Vectors. J. Electron. Test. Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos
2000	C	`conf`	MOSYS A Methodology for Automatic Object Identification from System Specification. ISORC Leandro Buss Becker, Carlos Eduardo Pereira, Octávio Páscoa Dias, Isabel C. Teixeira, João Paulo Teixeira
2000	—	`conf`	Optimizing Functional distribution in Complex System Design. DIPES Octávio Páscoa Dias, Isabel C. Teixeira, João Paulo Teixeira, Leandro Buss Becker, Carlos Eduardo Pereira
2000	—	`conf`	Quality of Electronic Design: From Architectural Level to Test Coverage. ISQED Octávio Páscoa Dias, Jorge Semião, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
2000	—	`conf`	RTL-based functional test generation for high defects coverage in digital SOCs. ETW Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
1999	A	`conf`	Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL. DATE Marcelino B. Santos, João Paulo Teixeira
1999	J	`jnl`	Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems. J. Electron. Test. Fernando M. Gonçalves, João Paulo Teixeira
1999	Misc	`conf`	Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique. VTS Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
1999	—	`conf`	From system level to defect-oriented test: a case study. ETW Octávio Páscoa Dias, Jorge Semião, Marcelino B. Santos, Isabel Maria Cacho Teixeira, João Paulo Teixeira
1999	—	`conf`	Low power BIST by filtering non-detecting vectors. ETW Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos
1999	—	`conf`	Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira, Marcelino B. Santos
1999	J	`jnl`	Metrics and Criteria for Quality Assessment of Testable Hw/Sw Systems Architectures. J. Electron. Test. Octávio Páscoa Dias, Isabel C. Teixeira, João Paulo Teixeira
1999	—	`conf`	Teaching Microelectronic-Based Integrated Systems Design and Test. MSE Fernando M. Gonçalves, João Paulo Teixeira
1998	—	`conf`	An OO Based Methodology for Real-Time HW/SW Systems Modeling. DIPES Octávio Páscoa Dias, Isabel C. Teixeira, João Paulo Teixeira, Carlos Eduardo Pereira
1998	A	`conf`	Defect-oriented test quality assessment using fault sampling and simulation. ITC Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
1998	—	`conf`	Defect-oriented testing of analogue and mixed signal ICs. ICECS Marcelino B. Santos, Fernando M. Gonçalves, Michael J. Ohletz, João Paulo Teixeira
1998	Misc	`conf`	Sampling Techniques of Non-Equally Probable Faults in VLSI System. VTS Fernando M. Gonçalves, João Paulo Teixeira
1997	—	`conf`	Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems. DFT Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
1996	J	`jnl`	Defect level evaluation in an IC design environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams
1996	A	`conf`	Defect-Oriented IC Test and Diagnosis Using VHDL Fault Simulation. ITC F. Celeiro, L. Dias, J. Ferreira, Marcelino B. Santos, João Paulo Teixeira
1996	C	`conf`	HW/SW specification using OOM techniques. RSP Mario Calha, João Paulo Teixeira, Isabel C. Teixeira
1996	—	`conf`	Integrated Approach for Circuit and Fault Extraction of VLSI Circuits. DFT Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
1996	—	`conf`	VHDL fault simulation for defect-oriented test and diagnosis of digital ICs. EURO-DAC João Paulo Teixeira, F. Celeiro, L. Dias, J. Ferreira, Marcelino B. Santos
1995	Misc	`conf`	Test preparation for high coverage of physical defects in CMOS digital ICs. VTS Marcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira
1995	—	`conf`	Test preparation methodology for high coverage of physical defects in CMOS digital ICs. ED&TC Marcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira
1994	A	`conf`	Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs. ITC Mario Calha, Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
1994	—	`conf`	Fault Modeling and Defect Level Projections in Digital ICs. EDAC-ETC-EUROASIC José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams
1994	—	`conf`	On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital Circuits. DFT A. P. Casimiro, Fernando M. Gonçalves, João Paulo Teixeira, Marcelino B. Santos
1993	—	`conf`	Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS Designs. DFT A. P. Casimiro, M. Simões, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
1993	—	`conf`	Realistic Fault Analysis of CMOS Analog Building Blocks. DFT P. Nicolau, J. Barbosa, M. Saraiva, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
1992	J	`jnl`	On the design of a highly testable cell library. Microprocess. Microprogramming M. Saraiva, Marcelino B. Santos, A. P. Casimiro, Isabel Maria Cacho Teixeira, João Paulo Teixeira
1992	A	`conf`	Physical DFT for High Coverage of Realistic Faults. ITC M. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
1991	J	`jnl`	A methodology for testability enhancement at layout level. J. Electron. Test. João Paulo Teixeira, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves
1991	A	`conf`	IC Defects-Based Testability Analysis. ITC José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira
1991	J	`jnl`	Physical design of testable CMOS digital integrated circuits. IEEE J. Solid State Circuits José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira
1990	—	`conf`	A strategy for testability enhancement at layout level. EURO-DAC João Paulo Teixeira, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves, R. Crespo