João Navarro Jr.

12 papers C 2Journal 2Unranked 8

Year	Rank	Type	Title / Venue / Authors
2011	—	`conf`	Design of high speed digital circuits with E-TSPC cell library. SBCCI João Navarro Jr., Gustavo Campos Martins
2007	C	`conf`	A 4.1 GHz Dual Modulus Prescaler Using the E-TSPC Technique and Double Data Throughput Structures. ISCAS Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije
2007	—	`conf`	A 4.1 GHz prescaler using double data throughput E-TSPC structures. SBCCI Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije
2007	—	`conf`	A small area 8bits 50MHz CMOS DAC for bluetooth transmitter. SBCCI Hugo Daniel Hernández, Wilhelmus A. M. Van Noije, Elkim Roa, João Navarro Jr.
2006	C	`conf`	Mismatch effect analyses in CMOS tapered buffers. ISCAS Alexandre J. Aragão, João Navarro Jr., Wilhelmus A. M. Van Noije
2005	—	`conf`	A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer. SBCCI Angel M. Gómez Argüello, João Navarro Jr., Wilhelmus A. M. Van Noije
2004	—	`conf`	A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35m CMOS technology. SBCCI Fernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije
2002	J	`jnl`	Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design. IEEE Trans. Very Large Scale Integr. Syst. João Navarro Jr., Wilhelmus A. M. Van Noije
1998	—	`conf`	CMOS Tapered Buffer Design for Small Width Clock/Data Signal Propagation. Great Lakes Symposium on VLSI João Navarro Jr., Wilhelmus A. M. Van Noije
1998	—	`conf`	Design of an 8: 1 MUX at 1.7Gbit/s in 0.8µm CMOS Technology. Great Lakes Symposium on VLSI João Navarro Jr., Wilhelmus A. M. Van Noije
1997	—	`conf`	A 1.4 Gbit/s CMOS driver for 50 Ω ECL systems. Great Lakes Symposium on VLSI João Navarro Jr., Reinaldo Silveira, Fábio L. Romao, Wilhelmus A. M. Van Noije
1995	J	`jnl`	Precise final state determination of mismatched CMOS latches. IEEE J. Solid State Circuits Wilhelmus A. M. Van Noije, W. T. Liu, João Navarro Jr.