João Canas Ferreira

65 papers A 4B 5C 11Misc 3Journal 24Unranked 18

Year	Rank	Type	Title / Venue / Authors
2021	J	`jnl`	A Binary Translation Framework for Automated Hardware Generation. IEEE Micro Nuno Paulino, João Bispo, João Canas Ferreira, João M. P. Cardoso
2021	J	`jnl`	A Flexible HLS Hoeffding Tree Implementation for Runtime Learning on FPGA. CoRR Luís Miguel Sousa, Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Bispo
2021	J	`jnl`	Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey. ACM Comput. Surv. Nuno Paulino, João Canas Ferreira, João M. P. Cardoso
2021	—	`conf`	On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators. FPT Tiago Santos, Nuno Paulino, João Bispo, João M. P. Cardoso, João Canas Ferreira
2020	J	`jnl`	A Dynamically Reconfigurable Dual-Waveform Baseband Modulator for Flexible Wireless Communications. J. Signal Process. Syst. Mário Lopes Ferreira, João Canas Ferreira
2020	J	`jnl`	A Multifunctional Integrated Circuit Router for Body Area Network Wearable Systems. IEEE/ACM Trans. Netw. Fardin Derogarian, João Canas Ferreira, Vítor M. Grade Tavares, José Machado da Silva, Fernando J. Velez
2020	B	`conf`	Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework. FPL Nuno Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso
2020	—	`conf`	Hardware architecture for integrate-and-fire signal reconstruction on FPGA. DCIS Guilherme Carvalho, João Canas Ferreira, Vítor Grade Tavares
2020	J	`jnl`	Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets. IEEE Access Nuno Paulino, João Canas Ferreira, João M. P. Cardoso
2020	J	`jnl`	Parallel Implementation of K-Means Algorithm on FPGA. IEEE Access Leonardo Alves Dias, João Canas Ferreira, Marcelo A. C. Fernandes
2019	J	`jnl`	Dynamic Partial Reconfiguration of Customized Single-Row Accelerators. IEEE Trans. Very Large Scale Integr. Syst. Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso
2019	J	`jnl`	Preface to the Special Issue on Methods, Tools, and Architectures for Signal and Image Processing. J. Signal Process. Syst. João Canas Ferreira, Francesca Palumbo
2018	—	`conf`	A Parallel-Pipelined OFDM Baseband Modulator with Dynamic Frequency Scaling for 5G Systems. ARC Mário Lopes Ferreira, João Canas Ferreira, Michael Hübner
2018	J	`jnl`	An FPGA array for cellular genetic algorithms: Application to the minimum energy broadcast problem. Microprocess. Microsystems Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira
2018	J	`jnl`	Analysis and Evaluation of anEnergy-Efficient Routing Protocol for WSNsCombining Source Routing and MinimumCost Forwarding. J. Mobile Multimedia Fardin Derogarian, João Canas Ferreira, Vítor M. Grade Tavares
2018	C	`conf`	Design and Evaluation of a Low Power CGRA Accelerator for Biomedical Signal Processing. DSD Helder H. Avelar, João Canas Ferreira
2018	C	`conf`	Flexible and Dynamically Reconfigurable FPGA-Based FS-FBMC Baseband Modulator. ISCAS Mário Lopes Ferreira, João Canas Ferreira
2017	—	`conf`	Evaluation of CGRA architecture for real-time processing of biological signals on wearable devices. ReConFig Joao Lopes, Diogo Sousa, João Canas Ferreira
2017	—	`conf`	FPGA-based implementation of a frequency spreading FBMC-OQAM baseband modulator. ICECS Miguel Carvalho, Mário Lopes Ferreira, João Canas Ferreira
2017	J	`jnl`	Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces. IEEE Trans. Very Large Scale Integr. Syst. Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso
2017	J	`jnl`	MICPRO DSD 2015 special issue. Microprocess. Microsystems João Canas Ferreira, Paris Kitsos
2017	—	`conf`	Towards a type 0 hypervisor for dynamic reconfigurable systems. ReConFig Benedikt Janßen, Fatih Korkmaz, Halil Derya, Michael Hübner, Mário Lopes Ferreira, João Canas Ferreira
2016	J	`jnl`	A small fully digital open-loop clock and data recovery circuit for wired BANs. Int. J. Circuit Theory Appl. Fardin Derogarian, João Canas Ferreira, Vítor Grade Tavares
2016	—	`conf`	An FPGA implementation of a long short-term memory neural network. ReConFig João Canas Ferreira, Jose Fonseca
2016	—	`conf`	Dynamically reconfigurable FFT processor for flexible OFDM baseband processing. DTIS Mário Lopes Ferreira, Amin Barahimi, João Canas Ferreira
2016	—	`conf`	Reconfigurable FPGA-Based FFT Processor for Cognitive Radio Applications. ARC Mário Lopes Ferreira, Amin Barahimi, João Canas Ferreira
2016	J	`jnl`	Scalable hardware architecture for disparity map computation and object location in real-time. J. Real Time Image Process. Pedro Miguel Salgueiro dos Santos, João Canas Ferreira, José Silva Matos
2015	J	`jnl`	A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses. ACM Trans. Reconfigurable Technol. Syst. Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso
2015	J	`jnl`	A time synchronization circuit with sub-microsecond skew for multi-hop wired wearable networks. Microprocess. Microsystems Fardin Derogarian, João Canas Ferreira, Vítor M. Grade Tavares
2015	C	`conf`	An FPGA Framework for Genetic Algorithms: Solving the Minimum Energy Broadcast Problem. DSD Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira
2015	C	`conf`	Reconfigurable NC-OFDM Processor for 5G Communications. EUC Mário Lopes Ferreira, João Canas Ferreira
2015	A	`conf`	Transparent acceleration of program execution using reconfigurable hardware. DATE Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso
2014	C	`conf`	A Time Synchronization Circuit with an Average 4.6 ns One-Hop Skew for Wired Wearable Networks. DSD Fardin Derogarian, João Canas Ferreira, Vítor M. Grade Tavares
2014	—	`conf`	Design and implementation of hybrid circuit/packet switching for wearable systems. ISIE Fardin Derogarian, João Canas Ferreira, Vítor Grade Tavares
2014	C	`conf`	Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support. ISPA Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Manuel Paiva Cardoso
2013	B	`conf`	A framework for hardware cellular genetic algorithms: An application to spectrum allocation in cognitive radio. FPL Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira
2013	—	`conf`	Architecture for Transparent Binary Acceleration of Loops with Memory Accesses. ARC Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso
2013	C	`conf`	Register Transfer Level Workflow for Application and Evaluation of Soft Error Mitigation Techniques. DSD Filipe Sousa, Francis Anghinolfi, João Canas Ferreira
2013	J	`jnl`	Special issue of Microelectronics Journal on the Conference on Design of Circuits and Integrated Systems 2011 (DCIS 2011). Microelectron. J. José Machado da Silva, Sylvie Renaud, João Canas Ferreira
2013	J	`jnl`	Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units. Int. J. Reconfigurable Comput. João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira
2013	J	`jnl`	Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems. IEEE Trans. Ind. Informatics João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira
2012	—	`conf`	A Wearable Sensor Network for Human Locomotion Data Capture. pHealth Andreina Zambrano, Fardin Derogarian, Ruben Dias, Maria José Abreu, André P. Catarino, Ana Maria Rocha, José Machado da Silva, João Canas Ferreira, Vítor Grade Tavares, Miguel Velhote Correia
2012	—	`conf`	A scalable array for Cellular Genetic Algorithms: TSP as case study. ReConFig Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira
2012	—	`conf`	Analysis of error detection schemes: Toolchain support and hardware/software implications. AHS Ali Azarian, João Canas Ferreira, Stephan Werner, Zlatko Petrov, João M. P. Cardoso, Michael Hübner
2012	C	`conf`	Design and Implementation of a Circuit for Mesh Networks with Application in Body Area Networks. DSD Fardin Derogarian, João Canas Ferreira, Vítor M. Grade Tavares
2012	J	`jnl`	Run-time generation of partial FPGA configurations for subword operations. Microprocess. Microsystems Miguel Lino Silva, João Canas Ferreira
2012	J	`jnl`	Run-time generation of partial FPGA configurations. J. Syst. Archit. Miguel Lino Silva, João Canas Ferreira
2011	—	`conf`	From Instruction Traces to Specialized Reconfigurable Arrays. ReConFig João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira
2010	C	`conf`	Creation of Partial FPGA Configurations at Run-Time. DSD Miguel Lino Silva, João Canas Ferreira
2010	B	`conf`	Erlang Inspired Hardware. FPL Paulo Ferreira, João Canas Ferreira, José Carlos Alves
2010	—	`conf`	FPGA-based rectification of stereo images. DASIP João G. P. Rodrigues, João Canas Ferreira
2008	B	`conf`	Generation of partial FPGA configurations at run-time. FPL Miguel Lino Silva, João Canas Ferreira
2007	J	`jnl`	Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems. IET Comput. Digit. Tech. Miguel Lino Silva, João Canas Ferreira
2006	A	`conf`	Exploiting dynamic reconfiguration of platform FPGAs: implementation issues. IPDPS Miguel L. Silva, João Canas Ferreira
2006	J	`jnl`	Support for partial run-time reconfiguration of platform FPGAs. J. Syst. Archit. Miguel Lino Silva, João Canas Ferreira
2005	A	`conf`	Run-Time Reconfiguration Support for FPGAs with Embedded CPUs: The Hardware Layer. IPDPS João Canas Ferreira, Miguel M. Silva
2005	C	`conf`	Using a Tightly-Coupled Pipeline in Dynamically Reconfigurable Platform FPGAs. DSD Miguel Lino Silva, João Canas Ferreira
2004	B	`conf`	A Development Support System for Applications That Use Dynamically Reconfigurable Hardware. FPL João Canas Ferreira, José Silva Matos
1999	Misc	`conf`	FAFNER-Accelerating Nesting Problems with FPGAs. FCCM José Carlos Alves, João Canas Ferreira, C. Albuquerque, José Fernando Oliveira, José Soeiro Ferreira, José Silva Matos
1998	Misc	`conf`	A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware. FCCM João Canas Ferreira, José Silva Matos
1998	—	`conf`	Flexible hardware acceleration for nesting problems. ICECS João Canas Ferreira, José Carlos Alves, Célio Albuquerque, José Fernando Oliveira, José Soeiro Ferreira, José Silva Matos
1998	—	`conf`	Mixed hardware/software applications on dynamically reconfigurable hardware. ICECS João Canas Ferreira, José Silva Matos
1994	C	`conf`	An Approach to Testability Improvement of Mixed-Signal Boards. ISCAS José Silva Matos, João Canas Ferreira, Ana C. Leão, José Machado da Silva
1994	Misc	`conf`	Architecture of test support ICs for mixed-signal testing. VTS José Silva Matos, João Canas Ferreira, Ana C. Leão, José Machado da Silva
1993	A	`conf`	Control and Observation of Analog Nodes in Mixed-Signal Boards. ITC José Silva Matos, Ana C. Leão, João Canas Ferreira