José Ángel Díaz-Madrid

16 papers A 1C 5Journal 7Unranked 3

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	An Efficient-Energy Charge-Domain Convolution Operator for CNN. IEEE Access José Ángel Díaz-Madrid, Ginés Doménech-Asensi, Ramón Ruiz Merino, Francisco Javier Andreo-Oliver
2025	C	`conf`	Interlaced 6T-10T CMOS in-memory computing circuit for low silicon area pipelined DNNs. ISCAS Ginés Doménech-Asensi, Francisco Javier Andreo-Oliver, Ramón Ruiz Merino, José Ángel Díaz-Madrid
2024	J	`jnl`	A real-time and energy-efficient SRAM with mixed-signal in-memory computing near CMOS sensors. J. Real Time Image Process. José Ángel Díaz-Madrid, Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez
2023	C	`conf`	A 12T SRAM in-Memory Computing differential current architecture for CNN implementations. ISCAS Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez, José Ángel Díaz-Madrid
2021	J	`jnl`	Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC. Circuits Syst. Signal Process. José Ángel Díaz-Madrid, Ginés Doménech-Asensi, J. Javier Martínez-Álvarez, Juan Zapata-Pérez, Ramón Ruiz Merino
2020	J	`jnl`	All-hardware SIFT implementation for real-time VGA images feature extraction. J. Real Time Image Process. Ginés Doménech-Asensi, Juan Zapata-Pérez, Ramón Ruiz Merino, José-Alejandro López Alcantud, José Ángel Díaz-Madrid, Víctor Manuel Brea Sánchez, Paula López
2020	C	`conf`	Mixed Signal Multiply and Adder Parallel Circuit for Deep Learning Convolution Operations. ISCAS José Ángel Díaz-Madrid, Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez, José Javier Martínez
2018	J	`jnl`	An all-hardware implementation of the subpixel refinement stage in SIFT algorithm. Int. J. Circuit Theory Appl. Pablo Rubio-Ibáñez, Ramón Ruiz Merino, Ginés Doménech-Asensi, J. Javier Martínez-Álvarez, Juan Zapata-Pérez, José Ángel Díaz-Madrid, José-Alejandro López Alcantud
2017	C	`conf`	An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation. ISCAS José Ángel Díaz-Madrid, Ginés Doménech-Asensi, José-Alejandro López Alcantud, M. Oberst
2013	J	`jnl`	Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels. Int. J. Circuit Theory Appl. Ginés Doménech-Asensi, José Ángel Díaz-Madrid, Ramón Ruiz Merino
2010	J	`jnl`	Fuzzy logic technique for accurate analog circuits macromodel sizing. Int. J. Circuit Theory Appl. José Ángel Díaz-Madrid, Juan Hinojosa, Ginés Doménech-Asensi
2009	A	`conf`	Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing. DATE José Ángel Díaz-Madrid, Harald Neubauer, Hans Hauer, Ginés Doménech-Asensi, Ramón Ruiz Merino
2008	C	`conf`	Accurate and reusable macromodeling technique using a fuzzy-logic approach. ISCAS Ginés Doménech-Asensi, Juan Hinojosa, Ramón Ruiz Merino, José Ángel Díaz-Madrid
2007	—	`conf`	Improvement of ANNs Performance to Generate Fitting Surfaces for Analog CMOS Circuits. IWINAC (2) José Ángel Díaz-Madrid, Pedro Monsalve-Campillo, Juan Hinojosa, María Victoria Rodellar Biarge, Ginés Doménech-Asensi
2003	—	`conf`	An Analogue Current-Mode Hardware Design Proposal for Preprocessing Layers in ART-Based Neural Networks. IWANN (2) José-Alejandro López Alcantud, José Ángel Díaz-Madrid, Hans Hauer, Ramón Ruiz Merino
2003	—	`conf`	Current Mode CMOS Synthesis of a Motor-Control Neural System. IWANN (2) Ginés Doménech-Asensi, Ramón Ruiz Merino, Hans Hauer, José Ángel Díaz-Madrid