José T. de Sousa

45 papers A* 1A 3B 9C 4Misc 4Journal 15Unranked 9

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Coarse-Grained Reconfigurable Arrays for High-Performance Low-Power Deep Neural Networks on Embedded Devices. DoCEIS João D. Lopes, Horácio C. Neto, José T. de Sousa
2024	C	`conf`	PT-Float: A Floating-Point Unit with Dynamically Varying Exponent and Fraction Sizes. ARITH José T. de Sousa, João D. Lopes, Micaela Serôdio, Horácio C. Neto, Mário P. Véstias
2023	J	`jnl`	Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units. ACM Trans. Reconfigurable Technol. Syst. Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2022	J	`jnl`	Onboard Processing of Synthetic Aperture Radar Backprojection Algorithm in FPGA. IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. David Mota, Helena Cruz, Pedro R. Miranda, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto, Mário P. Véstias
2021	J	`jnl`	A Full Featured Configurable Accelerator for Object Detection With YOLO. IEEE Access Daniel Pestana, Pedro R. Miranda, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa
2021	J	`jnl`	Configurable Hardware Core for IoT Object Detection. Future Internet Pedro R. Miranda, Daniel Pestana, João D. Lopes, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto, José T. de Sousa
2021	J	`jnl`	IOb-Cache: A High-Performance Configurable Open-Source Cache. Algorithms João V. Roque, João D. Lopes, Mário P. Véstias, José T. de Sousa
2020	J	`jnl`	A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs. IEEE Access Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2020	J	`jnl`	A fast and scalable architecture to run convolutional neural networks in low density FPGAs. Microprocess. Microsystems Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2020	—	`conf`	Implementing CNNs Using a Linear Array of Full Mesh CGRAs. ARC Valter Mário, João D. Lopes, Mário P. Véstias, José T. de Sousa
2020	J	`jnl`	Moving Deep Learning to the Edge. Algorithms Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2019	B	`conf`	Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA. FPL Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2019	C	`conf`	Low Energy Heterogeneous Computing with Multiple RISC-V and CGRA Cores. ISCAS Luís Fiolhais, Fernando M. Gonçalves, Rui Policarpo Duarte, Mário P. Véstias, José T. de Sousa
2018	B	`conf`	Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs. FPL Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2017	B	`conf`	K-means clustering on CGRA. FPL João D. Lopes, José T. de Sousa, Horácio C. Neto, Mário P. Véstias
2017	B	`conf`	Parallel dot-products for deep learning on FPGA. FPL Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa, Horácio C. Neto
2016	—	`conf`	Versat, a Minimal Coarse-Grain Reconfigurable Array. VECPAR João D. Lopes, José T. de Sousa
2015	C	`conf`	An ultra-low power low-IF GFSK demodulator for Bluetooth-LE applications. ISCAS Marco Silva Pereira, João Caldinhas Vaz, Carlos Azeredo Leme, José T. de Sousa, João Costa Freire
2008	J	`jnl`	Decision heuristic for Davis Putnam, Loveland and Logemann algorithm satisfiability solving based on cube subtraction. IET Comput. Digit. Tech. Romanelli Lodron Zuim, José T. de Sousa, Claudionor Coelho
2006	C	`conf`	A Fast SAT Solver Strategy Based on Negated Clauses. VLSI-SoC Romanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.
2006	—	`conf`	A fast SAT solver algorithm best suited to reconfigurable hardware. SBCCI Romanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.
2005	B	`conf`	A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits. FPL Victor Gonçalves, José T. de Sousa, Fernando M. Gonçalves
2005	J	`jnl`	Heuristic-Based Backtracking Relaxation for Propositional Satisfiability. J. Autom. Reason. Ateet Bhalla, Inês Lynce, José T. de Sousa, João Marques-Silva
2004	J	`jnl`	Guest Editors' Introduction: Field Programmable Logic and Applications. IEEE Trans. Computers Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa
2004	B	`conf`	Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor. FPL Carlos J. Tavares, C. Bungardean, G. M. Matos, José T. de Sousa
2003	B	`conf`	Fault Simulation Using Partially Reconfigurable Hardware. FPL Abilio Parreira, João Paulo Teixeira, A. Pantelimon, Marcelino B. Santos, José T. de Sousa
2003	B	`ed.`	Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings FPL Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa
2003	—	`conf`	Heuristic Backtracking Algorithms for SAT. MTV Ateet Bhalla, Inês Lynce, José T. de Sousa, João Marques-Silva
2003	Misc	`conf`	Heuristic-Based Backtracking for Propositional Satisfiability. EPIA Ateet Bhalla, Inês Lynce, José T. de Sousa, João Marques-Silva
2002	B	`conf`	DARP - A Digital Audio Reconfigurable Processor. FPL José T. de Sousa, Fernando M. Gonçalves, Nuno Barreiro, João Moura
2002	Misc	`conf`	On Implementing a Configware/Software SAT Solver. FCCM N. A. Reis, José T. de Sousa
2001	Misc	`conf`	A Configurable Hardware/Software Approach to SAT Solving. FCCM José T. de Sousa, J. M. da Silva, Miron Abramovici
2000	J	`jnl`	A SAT Solver Using Reconfigurable Hardware and Virtual Logic. J. Autom. Reason. Miron Abramovici, José T. de Sousa
2000	A	`conf`	Reducing the Complexity of Defect Level Modeling Using the Clustering Effect. DATE José T. de Sousa, Vishwani D. Agrawal
1999	A*	`conf`	A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware. DAC Miron Abramovici, José T. de Sousa, Daniel G. Saab
1999	Misc	`conf`	A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware. FCCM Miron Abramovici, José T. de Sousa
1999	—	`conf`	On Defect-Level Estimation and the Clustering Effect. VLSI José T. de Sousa
1997	J	`jnl`	Diagnosis of Boards for Realistic Interconnect Shorts. J. Electron. Test. José T. de Sousa, Peter Y. K. Cheung
1997	—	`conf`	Improved diagnosis of realistic interconnect shorts. ED&TC José T. de Sousa, Peter Y. K. Cheung
1996	J	`jnl`	Defect level evaluation in an IC design environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Cristoforo Marzocca, Francesco Corsi, Thomas W. Williams
1996	—	`conf`	Realistic Fault Extraction for Boards. ED&TC José T. de Sousa, T. Shen, Peter Y. K. Cheung
1994	—	`conf`	Fault Modeling and Defect Level Projections in Digital ICs. EDAC-ETC-EUROASIC José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira, Thomas W. Williams
1992	A	`conf`	Physical DFT for High Coverage of Realistic Faults. ITC M. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira
1991	A	`conf`	IC Defects-Based Testability Analysis. ITC José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira
1991	J	`jnl`	Physical design of testable CMOS digital integrated circuits. IEEE J. Solid State Circuits José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira