José Silva Matos

23 papers A 4B 1C 2Misc 5Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2016 J jnl
Scalable hardware architecture for disparity map computation and object location in real-time.
J. Real Time Image Process.
Pedro Miguel Salgueiro dos Santos, João Canas Ferreira, José Silva Matos
2015 J jnl
MICPRO DSD 2014 special issue.
Microprocess. Microsystems
Francesco Leporati, José Silva Matos
2014 J jnl
MICPRO DSD 2013 Special Issue.
Microprocess. Microsystems
José Silva Matos, Francesco Leporati
2005 C conf
A processor for testing mixed-signal cores in System-on-Chip.
DSD
Francisco Duarte, José Machado da Silva, José Carlos Alves, G. A. Pinho, José Silva Matos
2004 B conf
A Development Support System for Applications That Use Dynamically Reconfigurable Hardware.
FPL
João Canas Ferreira, José Silva Matos
2001 J jnl
ADC testing using joint time-frequency analysis.
Comput. Stand. Interfaces
Hélio Sousa Mendonça, José Machado da Silva, José Silva Matos
2000 A conf
Mixed-Signal BIST Using Correlation and Reconfigurable Hardware.
DATE
José Machado da Silva, J. Soeiro Duarte, José Silva Matos
1999 Misc conf
FAFNER-Accelerating Nesting Problems with FPGAs.
FCCM
José Carlos Alves, João Canas Ferreira, C. Albuquerque, José Fernando Oliveira, José Soeiro Ferreira, José Silva Matos
1998 Misc conf
A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware.
FCCM
João Canas Ferreira, José Silva Matos
1998 — conf
Computer Organisation, Programming and Benchmarking - Introduction.
VECPAR
José Silva Matos
1998 — conf
Flexible hardware acceleration for nesting problems.
ICECS
João Canas Ferreira, José Carlos Alves, Célio Albuquerque, José Fernando Oliveira, José Soeiro Ferreira, José Silva Matos
1998 — conf
Mixed hardware/software applications on dynamically reconfigurable hardware.
ICECS
João Canas Ferreira, José Silva Matos
1998 — conf
Mixed-Signal Board Level DfT Techniques Using IEEE P1149.4.
ICECS
José Silva Matos, José Machado da Silva
1998 Misc conf
RVC - A Reconfigurable Coprocessor for Vector Processing Applications.
FCCM
José Carlos Alves, José Silva Matos
1997 Misc conf
A vector architecture for higher-order moments estimation.
ICASSP
José Carlos Alves, André T. Puga, Luís Corte-Real, José Silva Matos
1997 A conf
Implementation of Mixed Current/Voltage Testing Using the IEEE P1149.4 Infrastructure.
ITC
José Machado da Silva, Ana C. Leão, José Silva Matos, José Carlos Alves
1996 — conf
Evaluation of iDD/vOUT Cross-Correlation for Mixed Current/Voltage Testing of Analogue and Mixed-Signal Circuits.
ED&TC
José Machado da Silva, José Silva Matos
1996 J jnl
Mixed current/voltage observation towards effective testing of analog and mixed-signal circuits.
J. Electron. Test.
José Machado da Silva, José Silva Matos, Ian M. Bell, Gaynor E. Taylor
1996 — conf
ProHos-1 - A Vector Processor for the Efficient Estimation of Higher-Order Moments.
VECPAR
José Carlos Alves, André T. Puga, Luís Corte-Real, José Silva Matos
1994 C conf
An Approach to Testability Improvement of Mixed-Signal Boards.
ISCAS
José Silva Matos, João Canas Ferreira, Ana C. Leão, José Machado da Silva
1994 Misc conf
Architecture of test support ICs for mixed-signal testing.
VTS
José Silva Matos, João Canas Ferreira, Ana C. Leão, José Machado da Silva
1993 A conf
Control and Observation of Analog Nodes in Mixed-Signal Boards.
ITC
José Silva Matos, Ana C. Leão, João Canas Ferreira
1992 A conf
A Boundary Scan Test Controller for Hierarchical BIST.
ITC
José M. M. Ferreira, Filipe S. Pinto, José Silva Matos